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| this is information on a product in full production. september 2013 doc id 14619 rev 12 1/117 1 spc560b40x, spc560b50x spc560c40x, spc560c50x 32-bit mcu family built on the power architecture ? for automotive body electronics applications datasheet ? production data features high-performance 64 mhz e200z0h cpu ? 32-bit power architecture ? technology ? up to 60 dmips operation ? variable length encoding (vle) memory ? up to 512 kb code flash with ecc ? 64 kb data flash with ecc ? up to 48 kb sram with ecc ? 8-entry memory protection unit (mpu) interrupts ? 16 priority levels ? non-maskable interrupt (nmi) ? up to 34 external interrupts incl. 18 wakeup lines gpio: 45(lqfp64), 75(lqfp100), 123(lqfp144) timer units ? 6-channel 32-bit periodic interrupt timers ? 4-channel 32-bit system timer module ? software watchdog timer ? real-time clock timer 16-bit counter time-triggered i/os ? up to 56 channels with pwm/mc/ic/oc ? adc diagnostic via ctu communications interface ? up to 6 flexcan interfaces (2.0b active) with 64-message objects each ? up to 4 linflex/uart ? 3 dspi / i2c single 5 v or 3.3 v supply 10-bit analog-to-digital converter (adc) with up to 36 channels ? extendable to 64 channels via external multiplexing ? individual conversion registers ? cross triggering unit (ctu) dedicated diagnostic module for lighting ? advanced pwm generation ? time-triggered diagnostic ? pwm-synchronized adc measurements clock generation ? 4 to 16 mhz fast external crystal oscillator (fxosc) ? 32 khz slow external crystal oscillator (sxosc) ? 16 mhz fast internal rc oscillator (firc) ? 128 khz slow internal rc oscillator (sirc) ? software-controlled fmpll ? clock monitor unit (cmu) exhaustive debugging capability ? nexus1 on all devices ? nexus2+ available on emulation package (lbga208) low power capabilities ? ultra-low power standby with rtc, sram and can monitoring ? fast wakeup schemes operating temp. range up to -40 to 125 c lqfp64 (10 x 10 x 1.4 mm) lqfp144 (20 x 20 x 1.4 mm) lqfp100 (14 x 14 x 1.4 mm) table 1. device summary package part number 256 kb code flash memory 512 kb code flash memory lqfp144 spc560b40l5 ? spc560b50l5 ? lqfp100 spc560b40l3 spc560c40l3 spc560b50l3 spc560c50l3 lqfp64 (1) spc560b40l1 spc560c40l1 spc560b50l1 spc560c50l1 1. all lqfp64information is indicative and must be confirmed during silicon validation. www.st.com
contents spc560b40x/50x, spc560c40x/50x 2/117 doc id 14619 rev 12 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.9 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.10 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.11 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.11.1 nvusro[pad3v5v] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.11.2 nvusro[oscillator_margin] field description . . . . . . . . . . . . . . . 39 3.11.3 nvusro[watchdog_en] field description . . . . . . . . . . . . . . . . . . . . 39 3.12 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.13 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.14 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.14.1 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.14.2 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.15 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.15.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.15.2 i/o input dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.15.3 i/o output dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.15.4 output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.15.5 i/o pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 spc560b40x/50x, spc560c40x/50x contents doc id 14619 rev 12 3/117 3.16 reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.17 power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 60 3.17.1 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 60 3.17.2 low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . 66 3.18 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.19 flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.19.1 program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.19.2 flash power supply dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.19.3 start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.20 electromagnetic compatibility (emc) characteristics . . . . . . . . . . . . . . . . 71 3.20.1 designing hardened software to avoid noise problems . . . . . . . . . . . . . 71 3.20.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.20.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 72 3.21 fast external crystal oscillator (4 to 16 mhz) electrical characteristics . . 73 3.22 slow external crystal oscillator (32 khz) electrical characteristics . . . . . . 76 3.23 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.24 fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . 80 3.25 slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . 81 3.26 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.26.2 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.26.3 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.27 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.27.1 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.27.2 dspi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.27.3 nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.27.4 jtag characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.1 lqfp64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.2 lqfp100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.3 lqfp144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.4 lbga208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 contents spc560b40x/50x, spc560c40x/50x 4/117 doc id 14619 rev 12 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 appendix a abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 spc560b40x/50x, spc560c40x/50x list of tables doc id 14619 rev 12 5/117 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc560b40x/50x and spc560c40x/50x device comparison . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. spc560b40x/50x and spc560c40x/50x series block summary . . . . . . . . . . . . . . . . . . . . 12 table 4. voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. system pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. pad3v5v field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 10. oscillator_margin field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. watchdog_en field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. recommended operating conditions (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. lqfp thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16. i/o input dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 17. i/o pull-up/pull-down dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18. slow configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. medium configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 48 table 20. fast configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. i/o supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. i/o consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 24. i/o weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 25. reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 26. voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 27. low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 28. power consumption on vdd_bv and vdd_hv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 29. program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 30. flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 31. flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 32. flash memory power supply dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 33. start-up time/switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 34. emi radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 35. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 36. latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 37. crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 38. fast external crystal oscillator (4 to 16 mhz) electrical characteristics. . . . . . . . . . . . . . . . 76 table 39. crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 40. slow external crystal oscillator (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . 78 table 41. fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 42. fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 80 table 43. slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 81 table 44. adc input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 45. adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 46. on-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 47. dspi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 48. nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 list of tables spc560b40x/50x, spc560c40x/50x 6/117 doc id 14619 rev 12 table 49. jtag characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 50. lqfp64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 51. lqfp100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 52. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 53. lbga208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 54. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 55. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 spc560b40x/50x, spc560c40x/50x list of figures doc id 14619 rev 12 7/117 list of figures figure 1. spc560b40x/50x and spc560c40x/50x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. lqfp 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. lqfp 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. lqfp 144-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. lbga208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. i/o input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 figure 7. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 8. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 9. voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 10. v dd_hv and v dd_bv maximum slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. v dd_hv and v dd_bv supply constraints during standby mode exit . . . . . . . . . . . . . . . . 63 figure 12. low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 13. crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 14. fast external crystal oscillator (4 to 16 mhz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 75 figure 15. crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 16. equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 17. slow external crystal oscillator (32 khz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 18. adc characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 19. input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 20. input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 21. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 22. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 23. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 24. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 25. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 26. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 27. dspi modified transfer format timing ? master, cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 28. dspi modified transfer format timing ? master, cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 29. dspi modified transfer format timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 30. dspi modified transfer format timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 31. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 32. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 33. timing diagram ? jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 34. lqfp64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 35. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 36. lqfp144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 37. lbga208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 38. commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 introduction spc560b40x/50x, spc560c40x/50x 8/117 doc id 14619 rev 12 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. to ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 description the spc560b40x/50x and spc560c40x/50x is a family of next generation microcontrollers built on the power architecture embedded category. the spc560b40x/50x and spc560c40x/50x family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. it belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. the advanced and cost-efficient host processor core of this automotive controller family complies with the power architecture embedded category and only implements the vle (variable-length encoding) apu, providing improved code density. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. spc560b40x/50x, spc560c40x/50x introduction doc id 14619 rev 12 9/117 table 2. spc560b40x/50x and spc560c40x/50x device comparison (1) feature device spc560b 40l1 spc560b 40l3 spc560b 40l5 spc560c 40l1 spc560c 40l3 spc560b 50l1 spc560b 50l3 spc560b 50l5 spc560c 50l1 spc560c 50l3 spc560b 50b2 cpu e200z0h execution speed (2) static ? up to 64 mhz code flash 256 kb 512 kb data flash 64 kb (4 16 kb) ram 24kb 32kb 32kb 48 kb mpu 8-entry adc (10-bit) 12 ch 28 ch 36 ch 8 ch 28 ch 12 ch 28 ch 36 ch 8 ch 28 ch 36 ch ctu yes total timer i/o (3) emios 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit ? pwm + mc + ic/oc (4) 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch ? pwm + ic/oc 4 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch ?ic/oc 4 ? 3ch 6ch ? 3ch ? 3ch 6ch ? 3ch 6ch sci (linflex) 3 (5) 4 spi (dspi) 2 3 2 3 2 3 2 3 can (flexcan) 2 (6) 56 3 (7) 56 i 2 c 1 32 khz oscillator yes gpio (8) 45 79 123 45 79 45 79 123 45 79 123 debug jtag nexus2+ package lqfp64 (9) lqfp100 lqfp144 lqfp64 9 lqfp100 lqfp64 9 lqfp100 lqfp144 lqfp64 9 lqfp100 lbga208 (10) introduction spc560b40x/50x, spc560c40x/50x 10/117 doc id 14619 rev 12 1. feature set dependent on selected peripheral mu ltiplexing?table shows example implementation 2. based on 125 c ambient operating temperature 3. see the emios section of the devic e reference manual for information on the channel configuration and functions. 4. ic ? input capture; oc ? output compare; pw m ? pulse width modulation; mc ? modulus counter 5. sci0, sci1 and sci2 are available. sci3 is not available. 6. can0, can1 are availabl e. can2, can3, can4 and can5 are not available. 7. can0, can1 and can2 are available. can3, can4 and can5 are not available. 8. i/o count based on multiplexing with peripherals 9. all lqfp64 information is indicative and must be confirmed during silicon validation. 10. lbga208 available only as development package for nexus2+ spc560b40x/50x, spc560c40x/50x block diagram doc id 14619 rev 12 11/117 2 block diagram figure 1 shows a top-level block diagram of the spc560b40x/50x and spc560c40x/50x device series. figure 1. spc560b40x/50x and spc560c40x/50x block diagram 3 x dspi fmpll nexus 2+ nexus sram siul reset control 48 kb external imux gpio and jtag pad control jtag port nexus port e200z0h interrupt requests 64-bit 2 x 3 crossbar switch 6 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . . . . . . . . . . intc i 2 c . . . 4 x linflex 2 x emios 36 ch. adc mpu cmu sram flash code flash 512 kb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module flexcan controller area network cmu clock monitor unit ctu cross triggering unit dspi deserial serial peripheral interface emios enhanced modular input output system fmpll frequency-modulated phase-locked loop i 2 c inter-integrated circuit bus imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) ecsm error correction status module mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module mpu memory protection unit nexus nexus development interface (ndi) level nmi non-maskable interrupt pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit mpu ecsm from peripheral registers blocks wkpu interrupt request with wakeup functionality block diagram spc560b40x/50x, spc560c40x/50x 12/117 doc id 14619 rev 12 ta ble 3 summarizes the functions of all blocks present in the spc560b40x/50x and spc560c40x/50x series of microcontrollers. please note that the presence and number of blocks vary by device and package. table 3. spc560b40x/50x and spc560c40x/50x series block summary block function analog-to-digital converter (adc) multi-channel, 10-bit analog-to-digital converter boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock monitor unit (cmu) monitors clock source (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels. enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol frequency-modulated phase- locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation internal multiplexer (imux) siu subblock allows flexible mapping of peripheral interface on the different pins of the device inter-integrated circuit (i 2 c?) bus a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load clock generation module (mc_cgm) provides logic and control required for the generation of system and peripheral clocks mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu spc560b40x/50x, spc560c40x/50x block diagram doc id 14619 rev 12 13/117 reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device memory protection unit (mpu) provides hardware access control for all memory references generated in a device nexus development interface (ndi) provides real-time development support capabilities in compliance with the ieee-isto 5001-2003 standard periodic interrupt timer (pit) produces periodic interrupts and triggers real-time counter (rtc) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) system integration unit (siu) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration static random-access memory (sram) provides storage for program code, constants, and variables system status configuration module (sscm) provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar (automotive open system architecture) and operating system tasks software watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) the wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. crossbar (xbar) switch supports simultaneous connections between two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. table 3. spc560b40x/50x and spc560c40x/50x series block summary (continued) block function package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 14/117 doc id 14619 rev 12 3 package pinouts and signal descriptions 3.1 package pinouts the available lqfp pinouts and the lbga208 ballmap are provided in the following figures. for pin signal descriptions, please refer to the device reference manual (rm0017). figure 2. lqfp 64-pin configuration (a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb[3] pc[9] pa[2] pa[1] pa[0] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa[9] pa[8] pa[7] pa[3] pb[15] pb[14] pb[13] pb[12] pb[11] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa[4] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pb[4] pb[2] pc[8] pc[4] pc[5] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] lqfp64 top view a.all lqfp64 information is indicative and must be confirmed during silicon validation. spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 15/117 figure 3. lqfp 100-pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa [2 ] pe[0] pa [1 ] pe[1] pe[8] pe[9] pe[10] pa [0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa[11] pa[10] pa[9] pa[8] pa[7] vdd_hv vss_hv pa[3] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] pe[12] lqfp100 note: availability of port pin alternate functions depends on product selection. to p vi e w package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 16/117 doc id 14619 rev 12 figure 4. lqfp 144-pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pb[3] pc[9] pc[14] pc[15] pg[5] pg[4] pg[3] pg[2] pa[2] pe[0] pa[1] pe[1] pe[8] pe[9] pe[10] pa[0] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pa[11] pa[10] pa[9] pa[8] pa[7] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa[3] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa[4] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [6 ] pa [5 ] pc[2] pc[3] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] lqfp144 note: availability of port pin alternate functions depends on product selection. top view spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 17/117 figure 5. lbga208 configuration 3.2 pad configuration during reset phases all pads have a fixed configuration under reset. during the power-up phase, all pads are forced to tristate. after power-up phase, all pads are forced to tristate with the following exceptions: pa[9] (fab) is pull-down. without external strong pull-up the device starts fetching from flash. pa[8] (abs[0]) is pull-up. reset pad is driven low. this is pull-up only after phase2 reset completion. jtag pads (tck, tms and tdi) are pull-up whilst tdo remains tristate. precise adc pads (pb[7:4] and pd[11:0]) are left tristate (no output buffer available). main oscillator pads (extal, xtal) are tristate. nexus output pads (mdo[ n ], mcko, evto, mseo) are forced to output. 12345678910111213141516 a pc[8] pc[13] nc nc ph[8] ph[4] pc[5] pc[0] nc nc pc[2] nc pe[15] nc nc nc a b pc[9] pb[2] nc pc[12] pe[6] ph[5] pc[4] ph[9] ph[10] nc pc[3] pg[11] pg[15] pg[14] pa[11] pa[10] b c pc[14] vdd_hv pb[3] pe[7] ph[7] pe[5] pe[3] vss_lv pc[1] nc pa[5] nc pe[14] pe[12] pa[9] pa[8] c d nc nc pc[15] nc ph[6] pe[4] pe[2] vdd_lv vdd_hv nc pa[6] nc pg[10] pf[14] pe[13] pa[7] d e pg[4] pg[5] pg[3] pg[2] pg[1] pg[0] pf[15] vdd_hv e f pe[0] pa[2] pa[1] pe[1] ph[0] ph[1] ph[3] ph[2] f g pe[9] pe[8] pe[10] pa[0] vss_hv vss_hv vss_hv vss_hv vdd_hv nc nc mseo g h vss_hv pe[11] vdd_hv nc vss_hv vss_hv vss_hv vss_hv mdo3 mdo2 mdo0 mdo1 h j reset vss_lv nc nc vss_hv vss_hv vss_hv vss_hv nc nc nc nc j k evti nc vdd_bv vdd_lv vss_hv vss_hv vss_hv vss_hv nc pg[12] pa[3] pg[13] k l pg[9] pg[8] nc evto pb[15] pd[15] pd[14] pb[14] l m pg[7] pg[6] pc[10] pc[11] pb[13] pd[13] pd[12] pb[12] m n pb[1] pf[9] pb[0] nc nc pa[4] vss_lv extal vdd_hv pf[0] pf[4] nc pb[11] pd[10] pd[9] pd[11] n p pf[8] nc pc[7] nc nc pa[14] vdd_lv xtal pb[10] pf[1] pf[5] pd[0] pd[3] vdd_hv _adc pb[6] pb[7] p r pf[12] pc[6] pf[10] pf[11] vdd_hv pa[15] pa[13] nc osc32k _xtal pf[3] pf[7] pd[2] pd[4] pd[7] vss_hv _adc pb[5] r t nc nc nc mcko nc pf[13] pa[12] nc osc32k _extal pf[2] pf[6] pd[1] pd[5] pd[6] pd[8] pb[4] t 12345678910111213141516 note: lbga208 available only as development package for nexus 2+. nc = not connected package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 18/117 doc id 14619 rev 12 3.3 voltage supply pins voltage supply pins are used to provide power to the device. three dedicated vdd_lv/vss_lv supply pairs are used for 1.2 v regulator stabilization. 3.4 pad types in the device the following types of pads are available for system pins and functional port pins: s = slow (b) m = medium b (c) f = fast b c i = input only with analog feature b j = input/output (?s? pad) with analog feature x = oscillator table 4. voltage supply pin descriptions port pin function pin number lqfp64 lqfp100 lqfp144 lbga208 (1) vdd_hv digital supply voltage 7, 28, 56 15, 37, 70, 84 19, 51, 100, 123 c2, d9, e16, g13, h3, n9, r5 vss_hv digital ground 6, 8, 26, 55 14, 16, 35, 69, 83 18, 20, 49, 99, 122 g7, g8, g9, g10, h1, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10 vdd_lv 1.2v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v ss_lv pin. (2) 11, 23, 57 19, 32, 85 23, 46, 124 d8, k4, p7 vss_lv 1.2v decoupling pins. decoupling capacitor must be connected between these pins and the nearest v dd_lv pin. 2 10, 24, 58 18, 33, 86 22, 47, 125 c8, j2, n7 vdd_bv internal regulator supply voltage 12 20 24 k3 vss_hv_ad c reference ground and analog ground for the adc 33 51 73 r15 vdd_hv_ad c reference voltage and analog supply for the adc 34 52 74 p14 1. lbga208 available only as development package for nexus2+ 2. a decoupling capacitor must be placed between each of the three vdd_lv/vss_lv supply pai rs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details). b.see the i/o pad electrical characteri stics in the device datasheet for details. c.all medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see pcr.src in section pad configuration regist ers (pcr0?pcr122) in the device reference manual). spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 19/117 3.5 system pins the system pins are listed in tab le 5 . 3.6 functional ports the functional port pins are listed in ta ble 6 table 5. system pin descriptions system pin function i/o direction pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (1) reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull-up only after phase2 91721j1 extal analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. analog input for the clock generator when the oscillator is in bypass mode. (2) i/o x tristate 27 36 50 n8 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator is used in bypass mode. 2 i x tristate 25 34 48 p8 1. lbga208 available only as development package for nexus2+ 2. see the relevant section of the datasheet table 6. functional port pin descriptions port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) pa[0] pcr[0] af0 af1 af2 af3 ? gpio[0] e0uc[0] clkout ? wkpu[19] (4) siul emios_0 cgl ? wkpu i/o i/o o ? i m tristate 5 12 16 g4 pa[1] pcr[1] af0 af1 af2 af3 ? ? gpio[1] e0uc[1] ? ? nmi (5) wkpu[2] 4 siul emios_0 ? ? wkpu wkpu i/o i/o ? ? i i stristate 4 7 11 f3 package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 20/117 doc id 14619 rev 12 pa[2] pcr[2] af0 af1 af2 af3 ? gpio[2] e0uc[2] ? ? wkpu[3] 4 siul emios_0 ? ? wkpu i/o i/o ? ? i stristate359f2 pa[3] pcr[3] af0 af1 af2 af3 ? gpio[3] e0uc[3] ? ? eirq[0] siul emios_0 ? ? siul i/o i/o ? ? i stristate436890k15 pa[4] pcr[4] af0 af1 af2 af3 ? gpio[4] e0uc[4] ? ? wkpu[9] 4 siul emios_0 ? ? wkpu i/o i/o ? ? i stristate202943n6 pa[5] pcr[5] af0 af1 af2 af3 gpio[5] e0uc[5] ? ? siul emios_0 ? ? i/o i/o ? ? mtristate 51 79 118c11 pa[6] pcr[6] af0 af1 af2 af3 ? gpio[6] e0uc[6] ? ? eirq[1] siul emios_0 ? ? siul i/o i/o ? ? i stristate 52 80119d11 pa[7] pcr[7] af0 af1 af2 af3 ? gpio[7] e0uc[7] lin3tx ? eirq[2] siul emios_0 linflex_3 ? siul i/o i/o o ? i s tristate 44 71 104 d16 pa[8] pcr[8] af0 af1 af2 af3 ? n/a (6) ? gpio[8] e0uc[8] ? ? eirq[3] abs[0] lin3rx siul emios_0 ? ? siul bam linflex_3 i/o i/o ? ? i i i s input, weak pull-up 45 72 105 c16 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 21/117 pa[9] pcr[9] af0 af1 af2 af3 n/a 6 gpio[9] e0uc[9] ? ? fab siul emios_0 ? ? bam i/o i/o ? ? i s pull-down 46 73 106 c15 pa[10] pcr[10] af0 af1 af2 af3 gpio[10] e0uc[10] sda ? siul emios_0 i2c_0 ? i/o i/o i/o ? s tristate 47 74 107 b16 pa[11] pcr[11] af0 af1 af2 af3 gpio[11] e0uc[11] scl ? siul emios_0 i2c_0 ? i/o i/o i/o ? s tristate 48 75 108 b15 pa[12] pcr[12] af0 af1 af2 af3 ? gpio[12] ? ? ? sin_0 siul ? ? ? dspi0 i/o ? ? ? i stristate223145t7 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 ? ? siul dspi_0 ? ? i/o o ? ? mtristate213044r7 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 ? eirq[4] siul dspi_0 dspi_0 ? siul i/o i/o i/o ? i mtristate192842p6 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 ? wkpu[10] 4 siul dspi_0 dspi_0 ? wkpu i/o i/o i/o ? i mtristate182740r6 pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx ? ? siul flexcan_ 0 ? ? i/o o ? ? mtristate142331n3 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 22/117 doc id 14619 rev 12 pb[1] pcr[17] af0 af1 af2 af3 ? ? gpio[17] ? ? ? wkpu[4] 4 can0rx siul ? ? ? wkpu flexcan_ 0 i/o ? ? ? i i stristate152432n1 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda ? siul linflex_0 i2c_0 ? i/o o i/o ? m tristate 64 100 144 b2 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] ? scl ? wkpu[11] 4 lin0rx siul ? i2c_0 ? wkpu linflex_0 i/o ? i/o ? i i stristate111c3 pb[4] pcr[20] af0 af1 af2 af3 ? gpio[20] ? ? ? gpi[0] siul ? ? ? adc i ? ? ? i itristate325072t16 pb[5] pcr[21] af0 af1 af2 af3 ? gpio[21] ? ? ? gpi[1] siul ? ? ? adc i ? ? ? i itristate355375r16 pb[6] pcr[22] af0 af1 af2 af3 ? gpio[22] ? ? ? gpi[2] siul ? ? ? adc i ? ? ? i itristate365476p15 pb[7] pcr[23] af0 af1 af2 af3 ? gpio[23] ? ? ? gpi[3] siul ? ? ? adc i ? ? ? i itristate375577p16 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 23/117 pb[8] pcr[24] af0 af1 af2 af3 ? ? gpio[24] ? ? ? ans[0] osc32k_xtal (7) siul ? ? ? adc sxosc i ? ? ? i i/o itristate303953r9 pb[9] pcr[25] af0 af1 af2 af3 ? ? gpio[25] ? ? ? ans[1] osc32k_extal 7 siul ? ? ? adc sxosc i ? ? ? i i/o itristate293852t9 pb[10] pcr[26] af0 af1 af2 af3 ? ? gpio[26] ? ? ? ans[2] wkpu[8] 4 siul ? ? ? adc wkpu i/o ? ? ? i i jtristate314054p9 pb[11] (8) pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 ans[3] siul emios_0 ? dspi_0 adc i/o i/o ? i/o i jtristate385981n13 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 anx[0] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate396183m16 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 anx[1] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate406385m13 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 anx[2] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate416587l16 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 24/117 doc id 14619 rev 12 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 anx[3] siul emios_0 ? dspi_0 adc i/o i/o ? o i jtristate426789l13 pc[0] (9) pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 59 87 126 a8 pc[1] 9 pcr[33] af0 af1 af2 af3 gpio[33] ? tdo (10) ? siul ? jtagc ? i/o ? o ? m tristate 54 82 121 c9 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx (11) ? eirq[5] siul dspi_1 flexcan_ 4 ? siul i/o i/o o ? i m tristate 50 78 117 a11 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] ? can1rx can4rx 11 eirq[6] siul dspi_1 adc ? flexcan_ 1 flexcan_ 4 siul i/o i/o o ? i i i s tristate 49 77 116 b11 pc[4] pcr[36] af0 af1 af2 af3 ? ? gpio[36] ? ? ? sin_1 can3rx 11 siul ? ? ? dspi_1 flexcan_ 3 i/o ? ? ? i i m tristate 62 92 131 b7 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 25/117 pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 can3tx 11 ? eirq[7] siul dspi1 flexcan_ 3 ? siul i/o o o ? i m tristate 61 91 130 a7 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx ? ? siul linflex_1 ? ? i/o o ? ? stristate162536r2 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? ? ? lin1rx wkpu[12] 4 siul ? ? ? linflex_1 wkpu i/o ? ? ? i i stristate172637p3 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx ? ? siul linflex_2 ? ? i/o o ? ? s tristate 63 99 143 a1 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? ? ? lin2rx wkpu[13] 4 siul ? ? ? linflex_2 wkpu i/o ? ? ? i i stristate222b1 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx 11 ma[1] siul flexcan_ 1 flexcan_ 4 adc i/o o o o mtristate132228m3 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 26/117 doc id 14619 rev 12 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ? can1rx can4rx 11 wkpu[5] 4 siul ? ? ? flexcan_ 1 flexcan_ 4 wkpu i/o ? ? ? i i i s tristate ? 21 27 m4 pc[12] pcr[44] af0 af1 af2 af3 ? gpio[44] e0uc[12] ? ? sin_2 siul emios_0 ? ? dspi_2 i/o i/o ? ? i m tristate ? 97 141 b4 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] sout_2 ? siul emios_0 dspi_2 ? i/o i/o o ? s tristate ? 98 142 a2 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] sck_2 ? eirq[8] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i stristate ? 3 3 c1 pc[15] pcr[47] af0 af1 af2 af3 gpio[47] e0uc[15] cs0_2 ? siul emios_0 dspi_2 ? i/o i/o i/o ? mtristate ? 4 4 d3 pd[0] pcr[48] af0 af1 af2 af3 ? gpio[48] ? ? ? gpi[4] siul ? ? ? adc i ? ? ? i i tristate ? 41 63 p12 pd[1] pcr[49] af0 af1 af2 af3 ? gpio[49] ? ? ? gpi[5] siul ? ? ? adc i ? ? ? i i tristate ? 42 64 t12 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 27/117 pd[2] pcr[50] af0 af1 af2 af3 ? gpio[50] ? ? ? gpi[6] siul ? ? ? adc i ? ? ? i i tristate ? 43 65 r12 pd[3] pcr[51] af0 af1 af2 af3 ? gpio[51] ? ? ? gpi[7] siul ? ? ? adc i ? ? ? i i tristate ? 44 66 p13 pd[4] pcr[52] af0 af1 af2 af3 ? gpio[52] ? ? ? gpi[8] siul ? ? ? adc i ? ? ? i i tristate ? 45 67 r13 pd[5] pcr[53] af0 af1 af2 af3 ? gpio[53] ? ? ? gpi[9] siul ? ? ? adc i ? ? ? i i tristate ? 46 68 t13 pd[6] pcr[54] af0 af1 af2 af3 ? gpio[54] ? ? ? gpi[10] siul ? ? ? adc i ? ? ? i i tristate ? 47 69 t14 pd[7] pcr[55] af0 af1 af2 af3 ? gpio[55] ? ? ? gpi[11] siul ? ? ? adc i ? ? ? i i tristate ? 48 70 r14 pd[8] pcr[56] af0 af1 af2 af3 ? gpio[56] ? ? ? gpi[12] siul ? ? ? adc i ? ? ? i i tristate ? 49 71 t15 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 28/117 doc id 14619 rev 12 pd[9] pcr[57] af0 af1 af2 af3 ? gpio[57] ? ? ? gpi[13] siul ? ? ? adc i ? ? ? i i tristate ? 56 78 n15 pd[10] pcr[58] af0 af1 af2 af3 ? gpio[58] ? ? ? gpi[14] siul ? ? ? adc i ? ? ? i i tristate ? 57 79 n14 pd[11] pcr[59] af0 af1 af2 af3 ? gpio[59] ? ? ? gpi[15] siul ? ? ? adc i ? ? ? i i tristate ? 58 80 n16 pd[12] 8 pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? ans[4] siul dspi_0 emios_0 ? adc i/o o i/o ? i j tristate ? 60 82 m15 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? ans[5] siul dspi_1 emios_0 ? adc i/o i/o i/o ? i j tristate ? 62 84 m14 pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? ans[6] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? 64 86 l15 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? ans[7] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? 66 88 l14 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 29/117 pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? can5rx 11 wkpu[6] 4 siul emios_0 ? ? flexcan_ 5 wkpu i/o i/o ? ? i i stristate ? 6 10 f1 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx 11 ? siul emios_0 flexcan_ 5 ? i/o i/o o ? mtristate ? 8 12 f4 pe[2] pcr[66] af0 af1 af2 af3 ? gpio[66] e0uc[18] ? ? sin_1 siul emios_0 ? ? dspi_1 i/o i/o ? ? i m tristate ? 89 128 d7 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios_0 dspi_1 ? i/o i/o o ? m tristate ? 90 129 c7 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios_0 dspi_1 ? siul i/o i/o i/o ? i m tristate ? 93 132 d6 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc i/o i/o i/o o m tristate ? 94 133 c6 pe[6] pcr[70] af0 af1 af2 af3 gpio[70] e0uc[22] cs3_0 ma[1] siul emios_0 dspi_0 adc i/o i/o o o m tristate ? 95 139 b5 pe[7] pcr[71] af0 af1 af2 af3 gpio[71] e0uc[23] cs2_0 ma[0] siul emios_0 dspi_0 adc i/o i/o o o m tristate ? 96 140 c4 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 30/117 doc id 14619 rev 12 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx (12) e0uc[22] can3tx 11 siul flexcan_ 2 emios_0 flexcan_ 3 i/o o i/o o mtristate ? 9 13 g2 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkpu[7] 4 can2rx 12 can3rx 11 siul ? emios_0 ? wkpu flexcan_ 2 flexcan_ 3 i/o ? i/o ? i i i s tristate ? 10 14 g1 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 ? eirq[10] siul linflex_3 dspi_1 ? siul i/o o o ? i stristate ? 11 15 g3 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] ? cs4_1 ? lin3rx wkpu[14] 4 siul ? dspi_1 ? linflex_3 wkpu i/o ? o ? i i s tristate ? 13 17 h2 pe[12] pcr[76] af0 af1 af2 af3 ? ? gpio[76] ? e1uc[19] (13) ? sin_2 eirq[11] siul ? emios_1 ? dspi_2 siul i/o ? i/o ? i i s tristate ? 76 109 c14 pe[13] pcr[77] af0 af1 af2 af3 gpio[77] sout2 e1uc[20] ? siul dspi_2 emios_1 ? i/o o i/o ? s tristate ? ? 103 d15 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 31/117 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i stristate ? ?112c13 pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] ? siul dspi_2 emios_1 ? i/o i/o i/o ? m tristate ? ? 113 a13 pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? ans[8] siul emios_0 dspi_1 ? adc i/o i/o o ? i jtristate ? ? 55n10 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? ans[9] siul emios_0 dspi_1 ? i i/o i/o o ? i jtristate ? ? 56p10 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? ans[10] siul emios_0 dspi_2 ? adc i/o i/o i/o ? i j tristate ? ? 57 t10 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? ans[11] siul emios_0 dspi_2 ? adc i/o i/o o ? i jtristate ? ? 58r10 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0uc[14] cs2_2 ? ans[12] siul emios_0 dspi_2 ? adc i/o i/o o ? i jtristate ? ? 59n11 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? ans[13] siul emios_0 dspi_2 ? adc i/o i/o o ? i jtristate ? ? 60p11 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 32/117 doc id 14619 rev 12 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] ? ? ans[14] siul emios_0 ? ? adc i/o i/o ? ? i jtristate ? ? 61t11 pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? ? ? ans[15] siul ? ? ? adc i/o ? ? ? i jtristate ? ? 62r11 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx (14) cs4_0 can2tx (15) siul flexcan_ 3 dspi_0 flexcan_ 2 i/o o o o mtristate ? ? 34 p1 pf[9] pcr[89] af0 af1 af2 af3 ? ? gpio[89] ? cs5_0 ? can2rx 15 can3rx 14 siul ? dspi_0 ? flexcan_ 2 flexcan_ 3 i/o ? o ? i i stristate ? ? 33 n2 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] ? ? ? siul ? ? ? i/o ? ? ? mtristate ? ? 38 r3 pf[11] pcr[91] af0 af1 af2 af3 ? gpio[91] ? ? ? wkpu[15] 4 siul ? ? ? wkpu i/o ? ? ? i stristate ? ? 39 r4 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] ? ? siul emios_1 ? ? i/o i/o ? ? mtristate ? ? 35 r1 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 33/117 pf[13] pcr[93] af0 af1 af2 af3 ? gpio[93] e1uc[26] ? ? wkpu[16] 4 siul emios_1 ? ? wkpu i/o i/o ? ? i stristate ? ? 41 t6 pf[14] pcr[94] af0 af1 af2 af3 gpio[94] can4tx 11 e1uc[27] can1tx siul flexcan_ 4 emios_1 flexcan_ 4 i/o o i/o o m tristate ? ? 102 d14 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? gpio[95] ? ? ? can1rx can4rx 11 eirq[13] siul ? ? ? flexcan_ 1 flexcan_ 4 siul i/o ? ? ? i i i s tristate ? ? 101 e15 pg[0] pcr[96] af0 af1 af2 af3 gpio[96] can5tx 11 e1uc[23] ? siul flexcan_ 5 emios_1 ? i/o o i/o ? mtristate ? ? 98e14 pg[1] pcr[97] af0 af1 af2 af3 ? ? gpio[97] ? e1uc[24] ? can5rx 11 eirq[14] siul ? emios_1 ? flexcan_ 5 siul i/o ? i/o ? i i stristate ? ? 97e13 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] ? ? siul emios_1 ? ? i/o i/o ? ? mtristate ? ? 8 e4 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 34/117 doc id 14619 rev 12 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] ? ? wkpu[17] 4 siul emios_1 ? ? wkpu i/o i/o ? ? i stristate ? ? 7 e3 pg[4] pcr[100 ] af0 af1 af2 af3 gpio[100] e1uc[13] ? ? siul emios_1 ? ? i/o i/o ? ? mtristate ? ? 6 e1 pg[5] pcr[101 ] af0 af1 af2 af3 ? gpio[101] e1uc[14] ? ? wkpu[18] 4 siul emios_1 ? ? wkpu i/o i/o ? ? i stristate ? ? 5 e2 pg[6] pcr[102 ] af0 af1 af2 af3 gpio[102] e1uc[15] ? ? siul emios_1 ? ? i/o i/o ? ? mtristate ? ? 30 m2 pg[7] pcr[103 ] af0 af1 af2 af3 gpio[103] e1uc[16] ? ? siul emios_1 ? ? i/o i/o ? ? mtristate ? ? 29 m1 pg[8] pcr[104 ] af0 af1 af2 af3 ? gpio[104] e1uc[17] ? cs0_2 eirq[15] siul emios_1 ? dspi_2 siul i/o i/o ? i/o i stristate ? ? 26 l2 pg[9] pcr[105 ] af0 af1 af2 af3 gpio[105] e1uc[18] ? sck_2 siul emios_1 ? dspi_2 i/o i/o ? i/o stristate ? ? 25 l1 pg[10] pcr[106 ] af0 af1 af2 af3 gpio[106] e0uc[24] ? ? siul emios_0 ? ? i/o i/o ? ? stristate ? ?114d13 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 35/117 pg[11] pcr[107 ] af0 af1 af2 af3 gpio[107] e0uc[25] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? ? 115 b12 pg[12] pcr[108 ] af0 af1 af2 af3 gpio[108] e0uc[26] ? ? siul emios_0 ? ? i/o i/o ? ? mtristate ? ? 92k14 pg[13] pcr[109 ] af0 af1 af2 af3 gpio[109] e0uc[27] ? ? siul emios_0 ? ? i/o i/o ? ? mtristate ? ? 91k16 pg[14] pcr[110 ] af0 af1 af2 af3 gpio[110] e1uc[0] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? ? 110 b14 pg[15] pcr[111] af0 af1 af2 af3 gpio[111] e1uc[1] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? 111 b13 ph[0] pcr[112 ] af0 af1 af2 af3 ? gpio[112] e1uc[2] ? ? sin1 siul emios_1 ? ? dspi_1 i/o i/o ? ? i m tristate ? ? 93 f13 ph[1] pcr[113 ] af0 af1 af2 af3 gpio[113] e1uc[3] sout1 ? siul emios_1 dspi_1 ? i/o i/o o ? m tristate ? ? 94 f14 ph[2] pcr[114 ] af0 af1 af2 af3 gpio[114] e1uc[4] sck_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? ? 95 f16 ph[3] pcr[115 ] af0 af1 af2 af3 gpio[115] e1uc[5] cs0_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? ? 96 f15 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 36/117 doc id 14619 rev 12 ph[4] pcr[116 ] af0 af1 af2 af3 gpio[116] e1uc[6] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? ? 134 a6 ph[5] pcr[117 ] af0 af1 af2 af3 gpio[117] e1uc[7] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? ? 135 b6 ph[6] pcr[118 ] af0 af1 af2 af3 gpio[118] e1uc[8] ? ma[2] siul emios_1 ? adc i/o i/o ? o m tristate ? ? 136 d5 ph[7] pcr[119 ] af0 af1 af2 af3 gpio[119] e1uc[9] cs3_2 ma[1] siul emios_1 dspi_2 adc i/o i/o o o m tristate ? ? 137 c5 ph[8] pcr[120 ] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc i/o i/o o o m tristate ? ? 138 a5 ph[9] 9 pcr[121 ] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 60 88 127 b8 ph[10] 9 pcr[122 ] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 53 81 120 b9 1. alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 00 af0; pcr.pa = 01 af1; pcr.pa = 10 af2; pcr.pa = 11 af3. this is intended to select the output functions; to use one of the input functions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2. multiple inputs are routed to all respective modules internally . the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 3. lbga208 available only as development package for nexus2+ 4. all wkpu pins also support external interrupt c apability. see wakeup unit chapter for further details. 5. nmi has higher priority than alternate function. when nmi is selected, the pcr.af field is ignored. 6. ?not applicable? because these functions are available only while the device is booting. refer to bam chapter of the reference manual for details. 7. value of pcr.ibe bit must be 0 table 6. functional port pin descriptions (continued) port pin pcr alternate function (1) function peripheral i/o direction (2) pad type reset configuration pin number lqfp64 lqfp100 lqfp144 lbga208 (3) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 37/117 3.7 nexus 2+ pins in the lbga208 package, eight additional debug pins are available (see table 7 ). 3.8 electrical characteristics 3.9 introduction this section contains electrical characteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to take precautions to avoid applying any voltage higher than the specified maximum rated voltages. 8. be aware that this pad is used on the spc560b64l 3 and spc560b64l5 to provide vdd_hv_adc and vss_hv_adc1. therefore, you should be careful in ensuring co mpatibility between spc560b40x/50x and spc560c40x/50x and spc560b64. 9. out of reset all the functional pins except pc[0:1] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). if the user configures these jtag pins in gpio mode the device is no longer compliant with ieee 1149.1-2001. 10. the tdo pad has been moved into the standby domain in order to allow low-power debug handshaking in standby mode. however, no pull-resistor is active on the tdo pad while in standby mode. at this time the pad is configured as an input. when no debugger is connected the tdo pad is floating caus ing additional current consumption. to avoid the extra consumption tdo must be connected. an exte rnal pull-up resistor in the range of 47?100 k should be added between the tdo pin and vdd_hv. only in case the tdo pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between tdo pin and gnd instead. 11. available only on spc560cx versions and spc560b50b2 devices 12. not available on spc560b40l3 and spc560b40l5 devices 13. not available in 100 lqfp package 14. available only on spc560b50b2 devices 15. not available on spc560b44l3 devices table 7. nexus 2+ pin descriptions debug pin function i/o direction pad type function after reset pin number lqfp 100 lqfp 144 lbga 208 (1) mcko message clock out o f ? ? ? t4 mdo0 message data out 0 o m ? ? ? h15 mdo1 message data out 1 o m ? ? ? h16 mdo2 message data out 2 o m ? ? ? h14 mdo3 message data out 3 o m ? ? ? h13 evti event in i m pull-up ? ? k1 evto event out o m ? ? ? l4 mseo message start/end out o m ? ? ? g16 1. lbga208 available only as development package for nexus2+ package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 38/117 doc id 14619 rev 12 to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent the characteristics of the device and its demands on the system. in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. caution: all lqfp64 information is indicative and must be confirmed during silicon validation. 3.10 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 8 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.11 nvusro register bit values in the non-volatile user options (nvusro) register control portions of the device configuration, namely electrical parameters such as high voltage supply and oscillator margin, as well as digital functionality (watchdog enable/disable after reset). for a detailed description of the nvusro register, please refer to the device reference manual. 3.11.1 nvusro[pad3v5v ] field description the dc electrical characteristics are dependent on the pad3v5v bit value. tab le 9 shows how nvusro[pad3v5v] controls the device configuration. table 8. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 39/117 3.11.2 nvusro[oscillator_ margin] field description the fast external crystal oscillator consumption is dependent on the oscillator_margin bit value. tab le 10 shows how nvusro[oscillator_margin] controls the device configuration. 3.11.3 nvusro[watchdog_en] field description the watchdog enable/disable configuration after reset is dependent on the watchdog_en bit value. tab le 11 shows how nvusro[watchdog_en] controls the device configuration. table 9. pad3v5v field description value (1) 1. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 10. oscillator_margin field description value (1) 1. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) table 11. watchdog_en field description value (1) 1. default manufacturing value is ?1?. value can be programmed by customer in shadow flash. description 0 disable after reset 1 enable after reset package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 40/117 doc id 14619 rev 12 3.12 absolute maximum ratings note: stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 42/117 doc id 14619 rev 12 note: ram data retention is guaranteed with v dd_lv not below 1.08 v. v dd (1) sr voltage on vdd_hv pins with respect to ground (v ss ) ?4.55.5 v voltage drop (2) 3.0 5.5 v ss_lv (3) sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss +0.1 v v dd_bv (4) sr voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ?4.55.5 v voltage drop 2 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v ss_adc sr voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ?v ss ? 0.1 v ss +0.1 v v dd_adc (5) sr voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?4.55.5 v voltage drop 2 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v in sr voltage on any gpio pin with respect to ground (v ss ) ?v ss ? 0.1 ? v relative to v dd ?v dd +0.1 i injpad sr injected input current on any pin during overload condition ? ? 55 ma i injsum sr absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd sr v dd slope to ensure correct power up (6) ?3.0 (7) 250 x 10 3 (0.25 [v/s]) v/s 1. 100 nf capacitance needs to be provided between each v dd /v ss pair. 2. full device operation is guaranteed by design when the voltage drops below 4.5 v down to 3.0 v. however, certain analog electrical characteristics will not be gua ranteed to stay within the stated limits. 3. 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4. 100 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regulator characteristics). 5. 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 6. guaranteed by device validation 7. minimum value of tv dd must be guaranteed until v dd reaches 2.6 v (maximum value of v porh ) table 14. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 43/117 3.14 thermal characteristics 3.14.1 package thermal characteristics table 15. lqfp thermal characteristics (1) symbol c parameter conditions (2) pin count value unit r ja cc d thermal resistance, junction-to- ambient natural convection (3) single-layer board - 1s 64 60 c/w 100 64 144 64 four-layer board - 2s2p 64 42 100 51 144 49 r jb cc d thermal resistance, junction-to- board (4) single-layer board - 1s 64 24 c/w 100 36 144 37 four-layer board - 2s2p 64 24 100 34 144 35 r jc cc d thermal resistance, junction-to- case (5) single-layer board - 1s 64 11 c/w 100 22 144 22 four-layer board - 2s2p 64 11 100 22 144 22 jb cc d junction-to-board thermal characterization parameter, natural convection single-layer board - 1s 64 tbd c/w 100 33 144 34 four-layer board - 2s2p 64 tbd 100 34 144 35 jc cc d junction-to-case thermal characterization parameter, natural convection single-layer board - 1s 64 tbd c/w 100 9 144 10 four-layer board - 2s2p 64 tbd 100 9 144 10 1. thermal characteristic s are based on simulation. 2. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 44/117 doc id 14619 rev 12 3.14.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : equation 1t j = t a + (p d x r ja ) where: t a is the ambient temperature in c. r ja is the package junction-to-ambient thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: equation 2p d = k / (t j + 273 c) therefore, solving equations 1 and 2 : equation 3k = p d x (t a + 273 c) + r ja x p d 2 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations 1 and 2 iteratively for any value of t a . 3. junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. 4. junction-to-board thermal resist ance determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 5. junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 45/117 3.15 i/o pad electrical characteristics 3.15.1 i/o pad types the device provides four main i/o pad types depending on the associated alternate functions: slow pads?these pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. medium pads?these pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. fast pads?these pads provide maximum speed. there are used for improved nexus debugging capability. input only pads?these pads are associated to adc channels and the external 32 khz crystal oscillator (sxosc) providing low input leakage. medium and fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing ac performance. 3.15.2 i/o input dc characteristics ta ble 16 provides input dc electrical characteristics as described in figure 6 . figure 6. i/o input dc electrical characteristics definition v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0? package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 46/117 doc id 14619 rev 12 3.15.3 i/o output dc characteristics the following tables provide dc characteristics for bidirectional pads: table 17 provides weak pull figures. both pull-up and pull-down resistances are supported. table 18 provides output driver characteristics for i/o pads when in slow configuration. table 19 provides output driver characteristics for i/o pads when in medium configuration. table 20 provides output driver characteristics for i/o pads when in fast configuration. table 16. i/o input dc electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih s r p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il s r p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v hys c c c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? i lkg c c d digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 200 na dt a =25 c ? 2 200 dt a =85 c ? 5 300 dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi (2) s r p wakeup input filtered pulse ? ? ? 40 ns w nfi 2 s r p wakeup input not filtered pulse ? 1000 ? ? ns 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. in the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. table 17. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions (1) value uni t min typ max |i wpu | c c p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 (2) 10 ? 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 47/117 |i wpd | c c p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 17. i/o pull-up/pull-down dc electrical characteristics (continued) symbol c parameter conditions (1) value uni t min typ max table 18. slow configuration output buffer electrical characteristics symbo l c parameter conditions (1) value uni t min typ max v o h c c p output high level slow configuration push pull i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v c i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v o l c c p output low level slow configuration push pull i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ??0.1v dd v c i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ??0.1v dd c i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 48/117 doc id 14619 rev 12 table 19. medium configuration output buffer electrical characteristics symbol c parameter conditions (1) value uni t min typ max v o h c c c output high level medium configuration push pull i oh = ? 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v p i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? c i oh = ? 1ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ?? c i oh = ? 100 a, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v o l c c c output low level medium configuration push pull i ol = 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 ?? 0.2v d d v p i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ?? 0.1v d d c i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ?? 0.1v d d c i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 c i ol = 100 a, v dd = 5.0 v 10%, pad3v5v = 0 ?? 0.1v d d 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 20. fast configuration output buffer electrical characteristics symbol c parameter conditions (1) value uni t min typ max v o h c c p output high level fast configuration push pull i oh = ? 14ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v c i oh = ? 7ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.8v dd ?? c i oh = ? 11ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 49/117 3.15.4 output pin transition times v o l c c p output low level fast configuration push pull i ol = 14ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ??0.1v dd v c i ol = 7ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ??0.1v dd c i ol = 11ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 20. fast configuration output buffer electrical characteristics (continued) symbol c parameter conditions (1) value uni t min typ max table 21. output pin transition times symbol c parameter conditions (1) value uni t mi n ty p ma x t tr cc d output transition time output pin (2) slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??50 tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 t tr cc d output transition time output pin 2 medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ??10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 t tr cc d output transition time output pin 2 fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 50/117 doc id 14619 rev 12 3.15.5 i/o pad current specification the i/o pads are distributed across the i/o supply segment. each i/o supply segment is associated to a v dd /v ss supply pair as described in ta ble 22 . ta ble 23 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a single segment should remain below the i avgseg maximum value. 2. c l includes device and package capacitances (c pkg < 5 pf). table 22. i/o supply segment package supply segment 123456 lbga208 (1) equivalent to lqfp144 segment pad distribution mcko mdon/mseo lqfp144 pin20?pin49 pin51?pin99 pin100?pin122 pin 123?pin19 ? ? lqfp100 pin16?pin35 pin37?pin69 pin70?pin83 pin 84?pin15 ? ? lqfp64 (2) pin8?pin26 pin28?pin55 pin56?pin7 ? ? ? 1. lbga208 available only as development package for nexus2+ 2. all lqfp64 information is indicative and must be confirmed during silicon validation. table 23. i/o consumption symbol c parameter conditions (1) value uni t min typ max i swtslw (2) c c d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20 ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed 2 c c d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29 ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst 2 c c d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??110 ma v dd = 3.3 v 10%, pad3v5v = 1 ??50 spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 51/117 ta ble 24 provides the weight of concurrent switching i/os. due to the dynamic current limitations, the sum of the weight of concurrent switching i/os on a single segment must not exceed 100% to ensure device functionality. i rmsslw c c d root mean square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3 ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed c c d root mean square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6 ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11 i rmsfst c c d root mean square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22 ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg s r d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to125 c, unless otherwise specified 2. stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 23. i/o consumption (continued) symbol c parameter conditions (1) value uni t min typ max package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 52/117 doc id 14619 rev 12 table 24. i/o weight (1) supply segment pad lqfp144/lqfp100 lqfp64 (2) weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 144 lqfp 100 lqfp 64 src (3) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1 4 4 3 pb[3] 10% ? 12% ? 10% ? 12% ? pc[9] 10% ? 12% ? 10% ? 12% ? ? pc[14 ] 9%?11%????? ? pc[15 ] 9%13%11%12%???? ? ?pg[5]9%?11%????? ? ?pg[4]9%12%10%11%???? ? ?pg[3]9%?10%????? 4 ? ?pg[2]8%12%10%10%???? 4 3 pa[2] 8% ? 9% ? 8% ? 9% ? ?pe[0]8%?9%????? 3 pa[1] 7% ? 9% ? 7% ? 9% ? ?pe[1]7%10%8%9%???? ?pe[8]7%9%8%8%???? ?pe[9]6%?7%????? ? pe[10 ] 6%?7%????? 3 pa[0] 5% 8% 6% 7% 5% 8% 6% 7% ? pe[11 ] 5%?6%????? spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 53/117 1 ??pg[9]9%?10%????? ? ?pg[8]9%?11%????? 1 ? pc[11 ] 9%?11%????? 1 pc[10 ] 9% 13% 11% 12% 9% 13% 11% 12% ? ?pg[7]10%14%11%12%???? ? ?pg[6]10%14%12%12%???? 11 pb[0] 10% 14% 12% 12% 10% 14% 12% 12% pb[1] 10% ? 12% ? 10% ? 12% ? ? ?pf[9]10%?12%????? ? ?pf[8]10%15%12%13%???? ? ? pf[12 ] 10%15%12%13%???? 11 pc[6] 10% ? 12% ? 10% ? 12% ? pc[7] 10% ? 12% ? 10% ? 12% ? ? ? pf[10 ] 10%14%12%12%???? ? ?pf[11]10%?11%????? 11 pa[15 ] 9% 12% 10% 11% 9% 12% 10% 11% ? ? pf[13 ] 8%?10%????? 11 pa[14 ] 8% 11% 9% 10% 8% 11% 9% 10% pa[4] 8% ? 9% ? 8% ? 9% ? pa[13 ] 7% 10% 9% 9% 7% 10% 9% 9% pa[12 ] 7% ? 8% ? 7% ? 8% ? table 24. i/o weight (1) (continued) supply segment pad lqfp144/lqfp100 lqfp64 (2) weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 144 lqfp 100 lqfp 64 src (3) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1 package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 54/117 doc id 14619 rev 12 2 22 pb[9] 1% ? 1% ? 1% ? 1% ? pb[8] 1% ? 1% ? 1% ? 1% ? pb[10 ] 6% ? 7% ? 6% ? 7% ? ? ?pf[0]6%?7%????? ? ?pf[1]7%?8%????? ? ?pf[2]7%?8%????? ? ?pf[3]7%?9%????? ? ?pf[4]8%?9%????? ? ?pf[5]8%?10%????? ? ?pf[6]8%?10%????? ? ?pf[7]9%?10%????? 2 ?pd[0]1%?1%????? ?pd[1]1%?1%????? ?pd[2]1%?1%????? ?pd[3]1%?1%????? ?pd[4]1%?1%????? ?pd[5]1%?1%????? ?pd[6]1%?1%????? ?pd[7]1%?1%????? ?pd[8]1%?1%????? 2 pb[4] 1% ? 1% ? 1% ? 1% ? pb[5] 1% ? 1% ? 1% ? 2% ? pb[6] 1% ? 1% ? 1% ? 2% ? pb[7] 1% ? 1% ? 1% ? 2% ? ?pd[9]1%?1%????? ? pd[10 ] 1%?1%????? ? pd[11 ] 1%?1%????? 2 pb[11 ] 11% ? 13% ? 17% ? 21% ? ? pd[12 ] 11%?13%????? table 24. i/o weight (1) (continued) supply segment pad lqfp144/lqfp100 lqfp64 (2) weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 144 lqfp 100 lqfp 64 src (3) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1 spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 55/117 2 2 2 pb[13 ] 10% ? 12% ? 18% ? 21% ? ? pd[14 ] 10%?12%????? 2 pb[14 ] 10% ? 12% ? 18% ? 21% ? ? pd[15 ] 10%?11%????? 2 pb[15 ] 9% ? 11% ? 18% ? 21% ? pa[3] 9% ? 11% ? 18% ? 21% ? ? ? pg[13 ] 9%13%10%11%???? ? ? pg[12 ] 9%12%10%11%???? ? ?ph[0]5%8%6%7%???? ? ?ph[1]5%7%6%6%???? ? ?ph[2]5%6%5%6%???? ? ?ph[3]4%6%5%5%???? ? ?pg[1]4%?4%????? ? ?pg[0]3%4%4%4%???? table 24. i/o weight (1) (continued) supply segment pad lqfp144/lqfp100 lqfp64 (2) weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 144 lqfp 100 lqfp 64 src (3) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1 package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 56/117 doc id 14619 rev 12 3 ?? pf[15 ] 3%?4%????? ? ? pf[14 ] 4%5%5%5%???? ? ? pe[13 ] 4%?5%????? 3 2 pa[7] 5% ? 6% ? 16% ? 19% ? pa[8] 5% ? 6% ? 16% ? 19% ? pa[9] 5% ? 6% ? 15% ? 18% ? pa[10 ] 6% ? 7% ? 15% ? 18% ? pa[11] 6% ? 8% ? 14% ? 17% ? ? pe[12 ] 7%?8%????? ? ? pg[14 ] 7%?8%????? ? ? pg[15 ] 7%10%8%9%???? ? ? pe[14 ] 7%?8%????? ? ? pe[15 ] 7%9%8%8%???? ? ? pg[10 ] 6%?8%????? ? ? pg[11 ] 6%9%7%8%???? 32 pc[3] 6% ? 7% ? 7% ? 9% ? pc[2]6% 8%7%7%6%9%8%8% 33 2 pa[5]5% 7%6%6%6%8%7%7% pa[6] 5% ? 6% ? 5% ? 6% ? ph[10 ] 4% 6% 5% 5% 5% 7% 6% 6% pc[1] 5% ? 5% ? 5% ? 5% ? table 24. i/o weight (1) (continued) supply segment pad lqfp144/lqfp100 lqfp64 (2) weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 144 lqfp 100 lqfp 64 src (3) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1 spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 57/117 4 4 3 pc[0]6% 9%7%8%6%9%7%8% ph[9]7 7887788 ?pe[2]7%10%9%9%???? ?pe[3]8%11%9%9%???? 3 pc[5] 8% 11% 9% 10% 8% 11% 9% 10% pc[4] 8% 12% 10% 10% 8% 12% 10% 10% ?pe[4]8%12%10%11%???? ?pe[5]9%12%10%11%???? ? ?ph[4]9%13%11%11%???? ? ?ph[5]9%?11%????? ? ?ph[6]9%13%11%12%???? ? ?ph[7]9%13%11%12%???? ? ?ph[8]10%14%11%12%???? 4 ?pe[6]10%14%12%12%???? ?pe[7]10%14%12%12%???? ? pc[12 ] 10%14%12%13%???? ? pc[13 ] 10%?12%????? 3 pc[8] 10% ? 12% ? 10% ? 12% ? pb[2] 10% 15% 12% 13% 10% 15% 12% 13% 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to125 c, unless otherwise specified 2. all lqfp64 information is indicative and must be confirmed during silicon validation. 3. src: ?slew rate control? bit in siu_pcr table 24. i/o weight (1) (continued) supply segment pad lqfp144/lqfp100 lqfp64 (2) weight 5 v weight 3.3 v weight 5 v weight 3.3 v lqfp 144 lqfp 100 lqfp 64 src (3) = 0 src = 1 src = 0 src = 1 src = 0 src = 1 src = 0 src = 1 package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 58/117 doc id 14619 rev 12 3.16 reset electrical characteristics the device implements a dedicated bidirectional reset pin. figure 7. start-up reset requirements figure 8. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 59/117 table 25. reset electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih s r p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il s r p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys c c c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol c c p output low level push pull, i ol = 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v c push pull, i ol = 1ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd c push pull, i ol = 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr c c d output transition time output pin (3) c l = 25pf, v dd = 5.0 v 10%, pad3v5v = 0 ??10 ns c l = 50pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 c l = 100pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 c l = 25pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 c l = 50pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 c l = 100pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst s r p reset input filtered pulse ???40ns w nfrs t s r p reset input not filtered pulse ? 1000 ? ? ns |i wpu | c c p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a dv dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 pv dd = 5.0 v 10%, pad3v5v = 1 2 10 ? 250 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. this transient configuration does not occurs when device is used in the v dd = 3.3 v 10% range. 3. c l includes device and package capacitance (c pkg <5pf). package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 60/117 doc id 14619 rev 12 3.17 power management electrical characteristics 3.17.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage ballast supply v dd_bv . the regulator itself is supplied by the common i/o supply v dd . the following supplies are involved: hv?high voltage external power supply for voltage regulator module. this must be provided externally through vdd_hv power pin. bv?high voltage external power supply for internal ballast module. this must be provided externally through vdd_bv power pin. voltage values should be aligned with v dd . lv?low voltage internal power supply for core, fmpll and flash digital logic. this is generated by the internal voltage regulator but provided outside to connect stability capacitor. it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor?low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla?low voltage supply for code flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_dfla?low voltage supply for data flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_pll?low voltage supply for fmpll. it is shorted to lv_cor through double bonding. spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 61/117 figure 9. voltage regulator capacitance connection the internal voltage regulator requires external capacitance (c regn ) to be connected to the device in order to provide a stable low voltage digital supply to the device. capacitances should be placed on the board as near as possible to the associated pins. care should also be taken to limit the serial inductance of the board to less than 5 nh. each decoupling capacitor must be placed between each of the three v dd_lv /v ss_lv supply pairs to ensure stable voltage (see section 3.13, recommended operating conditions ). c reg1 (lv_cor/lv_dfla) device vss_lv vdd_bv vdd_lv c dec1 (ballast decoupling) vss_lv vdd_lv vdd_hv vss_lv vdd_lv c reg2 (lv_cor/lv_cfla) c reg3 c dec2 device vdd_bv i vdd_lvn v ref vdd_hv voltage regulator vss_hv vss_lvn (supply/io decoupling) (lv_cor/lv_pll) package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 62/117 doc id 14619 rev 12 the internal voltage regulator requires a controlled slew rate of both v dd_hv and v dd_bv as described in figure 10 . figure 10. v dd_hv and v dd_bv maximum slope when standby mode is used, further constraints are applied to the both v dd_hv and v dd_bv in order to guarantee correct regulator function during standby exit. this is described on figure 11 . standby regulator constraints should normally be guaranteed by implementing equivalent of cstdby capacitance on application board (capacitance and esr typical values), but would actually depend on exact characteristics of application external regulator. v dd_hv t d d vdd power up power down v dd_hv (max) functional range v porh (max) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 63/117 figure 11. v dd_hv and v dd_bv supply constraints during standby mode exit v dd_hv v dd_hv (min) vdd(stdby) v dd_hv v dd_hv (max) v dd_lv t d d vdd stdby () d d vdd stdby () vdd(stdby) v dd_lv (nominal) 0v table 26. voltage regulator electrical characteristics symbol c parameter conditions (1) value unit min typ max c regn s r ? internal voltage regulator external capacitance ? 200 ? 500 nf r reg s r ? stability capacitor equivalent serial resistance range: 10 khz to 20 mhz ??0.2 c dec1 s r ? decoupling capacitance (2) ballast v dd_bv /v ss_lv pair: v dd_bv = 4.5 v to 5.5 v 100 (3) 470 (4) ? nf v dd_bv /v ss_lv pair: v dd_bv = 3 v to 3.6 v 400 ? c dec2 s r ? decoupling capacitance regulator supply v dd /v ss pair 10 100 ? nf s r ? maximum slope on v dd ??250 mv/ s | vdd(stdby) | s r ? maximum instant variation on v dd during standby exit ??30mv t d d vdd package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 64/117 doc id 14619 rev 12 s r ? maximum slope on v dd during standby exit ??15 mv/ s v mreg c c t main regulator output voltage before exiting from reset ? 1.32 ? v p after trimming 1.16 1.28 ? i mreg s r ? main regulator current provided to v dd_lv domain ??? 150 ma i mregint c c d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg c c p low power regulator output voltage after trimming 1.16 1.28 ? v i lpreg s r ? low power regulator current provided to v dd_lv domain ??? 15 ma i lpregint c c d low power regulator module current consumption i lpreg = 15 ma; t a = 55 c ?? 600 a ? i lpreg = 0 ma; t a = 55 c ? 5? v ulpreg c c p ultra low power regulator output voltage after trimming 1.16 1.28 ? v i ulpreg s r ? ultra low power regulator current provided to v dd_lv domain ??? 5 ma i ulpregint c c d ultra low power regulator module current consumption i ulpreg = 5 ma; t a = 55 c ?? 100 a i ulpreg = 0 ma; t a = 55 c ? 2? i dd_bv c c d in-rush average current on v dd_bv during power-up (5) ?? ? 300 (6) ma 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. this capacitance value is driven by the constraints of the exter nal voltage regulator supplying the v dd_bv voltage. a typical value is in the range of 470 nf. 3. this value is acceptable to guarantee operation from 4.5 v to 5.5 v 4. external regulator and capacitance circ uitry must be capable of providing i dd_bv while maintaining supply v dd_bv in operating range. 5. in-rush average current is seen only for short time (maximum 20 s) during power-up and on standby exit. it is dependant on the sum of the c regn capacitances. 6. the duration of the in-rush current depends on the capacitance placed on lv pins. bv decoupling capacitors must be sized accordingly. refer to i mreg value for minimum amount of current to be provided in cc. table 26. voltage regulator electrical characteristics (continued) symbol c parameter conditions (1) value unit min typ max t d d vdd stdby () spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 65/117 the | vdd(stdby) | and dvdd(stdby)/dt system requirement can be used to define the component used for the v dd supply generation. the following two examples describe how to calculate capacitance size: example 1 no regulator (worst case) the | vdd(stdby) | parameter can be seen as the v dd voltage drop through the esr resistance of the regulator stability capacitor when the i dd_bv current required to load v dd_lv domain during the standby exit. it is thus possible to define the maximum equivalent resistance esr stdby (max) of the total capacitance on the v dd supply: esr stdby (max) = | vdd(stdby) |/i dd_bv = (30 mv)/(300 ma) = 0.1 (d) the dvdd(stdby)/dt parameter can be seen as the v dd voltage drop at the capacitance pin (excluding esr drop) while providing the i dd_bv supply required to load v dd_lv domain during the standby exit. it is thus possible to define the minimum equivalent capacitance c stdby (min) of the total capacitance on the v dd supply: c stdby (min) = i dd_bv /dvdd(stdby)/dt = (300 ma)/(15 mv/s) = 20 f this configuration is a worst case, with the assumption no regulator is available. example 2 simplified regulator the regulator should be able to provide significant amount of the current during the standby exit process. for example, in case of an ideal voltage regulator providing 200 ma current, it is possible to recalculate the equivalent esr stdby (max) and c stdby (min) as follows: esr stdby (max) = | vdd(stdby) |/(i dd_bv ? 200 ma) = (30 mv)/(100 ma) = 0.3 c stdby (min) = (i dd_bv ? 200 ma)/dvdd(stdby)/dt = (300 ma ? 200 ma)/(15 mv/s) = 6.7 f in case optimization is required, c stdby (min) and esr stdby (max) should be calculated based on the regulator characteristics as well as the board v dd plane characteristics. d.based on typical time for standby exit sequence of 20 s , esr(min) can actually be considered at ~50 khz. package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 66/117 doc id 14619 rev 12 3.17.2 low voltage detector electrical characteristics the device implements a power-on reset (por) module to ensure correct power-up initialization, as well as four low voltage detectors (lvds) to monitor the v dd and the v dd_lv voltage while device is supplied: por monitors v dd during the power-up phase to ensure device is maintained in a safe reset state (refer to rgm destructive event status (rgm_des) register flag f_por in device reference manual) lvdhv3 monitors v dd to ensure device reset below minimum functional supply (refer to rgm destructive event status (rgm_des) register flag f_lvd27 in device reference manual) lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range (refer to rgm functional event status (rgm_fes) register flag f_lvd45 in device reference manual) lvdlvcor monitors power domain no. 1 (refer to rgm destructive event status (rgm_des) register flag f_lvd12_pd1 in device reference manual lvdlvbkp monitors power domain no. 0 (refer to rgm destructive event status (rgm_des) register flag f_lvd12_pd0 in device reference manual) note: when enabled, power domain no. 2 is monitored through lvdlvbkp. figure 12. low voltage detector vs reset v dd v lvdhvxh reset v lvdhvxl spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 67/117 3.18 power consumption ta ble 28 provides dc electrical characteristics for significant application modes. these values are indicative values; actual consumption depends on the application. table 27. low voltage detector electrical characteristics symbol c parameter conditions (1) value uni t min typ max v porup s r p supply for functional por module ? 1.0 ? 5.5 v v porh c c p power-on reset threshold t a = 25 c, after trimming 1.5 ? 2.6 t ? 1.5 ? 2.6 v lvdhv3h c c t lvdhv3 low voltage detector high threshold ? ??2.95 v lvdhv3l c c p lvdhv3 low voltage detector low threshold 2.6 ? 2.9 v lvdhv5h c c t lvdhv5 low voltage detector high threshold ? ? 4.5 v lvdhv5l c c p lvdhv5 low voltage detector low threshold 3.8 ? 4.4 v lvdlvcorl c c p lvdlvcor low voltage detector low threshold 1.08 ? 1.16 v lvdlvbkpl c c p lvdlvbkp low voltage detector low threshold 1.08 ? 1.16 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified table 28. power consumption on vdd_bv and vdd_hv symbol c parameter conditions (1) value uni t min typ max i ddmax (2) c c d run mode maximum average current ??115140 (3) ma i ddrun (4) c c t run mode typical average current (5) f cpu = 8 mhz ? 7 ? ma tf cpu = 16 mhz ? 18 ? tf cpu = 32 mhz ? 29 ? pf cpu = 48 mhz ? 40 100 pf cpu = 64 mhz ? 51 125 i ddhalt c c c halt mode current (6) slow internal rc oscillator (128 khz) running t a =25c ? 8 15 ma p t a = 125 c ?14 25 package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 68/117 doc id 14619 rev 12 i ddstop c c p stop mode current (7) slow internal rc oscillator (128 khz) running t a = 25 c ? 180 700 (8) a dt a = 55 c ? 500 ? dt a =85c ? 1 6 8 ma d t a = 105 c ?2 9 8 p t a = 125 c ?4.512 8 i ddstdby2 c c p standby2 mode current (9) slow internal rc oscillator (128 khz) running t a =25c ? 30 100 a dt a =55c ? 75 ? dt a = 85 c ? 180 700 d t a = 105 c ? 315 1000 p t a = 125 c ? 560 1700 i ddstdby1 c c t standby1 mode current (10) slow internal rc oscillator (128 khz) running t a = 25 c ? 20 60 a dt a =55c ? 45 ? dt a = 85 c ? 100 350 d t a = 105 c ? 165 500 d t a = 125 c ? 280 900 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. i ddmax is drawn only from the v dd_bv pin. running consumption does not include i/os toggling which is highly dependent on the application. the given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation ongoing on data flash. notice that th is value can be significantly r educed by application: switch off not used peripherals (default), reduce peripheral frequency through internal pres caler, fetch from ram most used functions, use low power mode when possible. 3. higher current may be sinked by dev ice during power-up and standby exit. please refer to in rush current on table 26 . 4. i ddrun is drawn only from the v dd_bv pin. run current measured with typical application with accesses on both flash and ram. 5. only for the ?p? classification: data and code flash in normal power. code fetched from ram: serial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x m ultiplier) peripherals on (emios/ctu/adc) and running at max frequency, periodic sw/wdg timer reset enabled. 6. data flash power down. code flash in low power. sirc (128 khz) and firc (16 mhz) on. 10 mhz xtal clock. flexcan: instances: 0, 1, 2 on (clocked but not rec eption or transmission), instances: 4, 5, 6 clock gated. linflex: instances: 0, 1, 2 on (clocked but not reception or transmission), instance: 3 clock gated. emios: instance: 0 on (16 channels on pa[0]? pa[11] and pc[12]?pc[15]) with pwm 20 khz, instance: 1 cl ock gated. dspi: instance: 0 (clocked but no communication). rtc/api on. pit on. stm on. adc on but not conversion except 2 analog watchdog. 7. only for the ?p? classification: no clock, firc (16 mhz) off, sirc (128 khz) on, pll off, hpvreg off, ulpvreg/lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 8. when going from run to stop mode and the core consumption is > 6 ma, it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. this is most likely to occur with junction temperatures exceeding 125 c and under these circumstances, it is possible for the current to initially exceed the maximum stop specification by up to 2 ma. after entering stop, the applicatio n junction temperature will reduc e to the ambient level and the main regulator will be automatically switc hed off when the load current is below 6 ma. table 28. power consumption on vdd_bv and vdd_hv (continued) symbol c parameter conditions (1) value uni t min typ max spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 69/117 3.19 flash memory electrical characteristics 3.19.1 program/erase characteristics ta ble 29 shows the program and erase characteristics. 9. only for the ?p? classification: ulpreg on, hp/lpvreg off, 32 kb ram on, device configured for minimum consumption, all possible modules switched off. 10. ulpreg on, hp/lpvreg off, 8 kb ram on, device configured fo r minimum consumption, all possible modules switched off. table 29. program and erase specifications symbol c parameter value uni t min typ (1) initial max (2) max (3) t dwprogram c c c double word (64 bits) program time (4) ?2250500s t 16kpperase 16 kb block preprogram and erase time ? 300 500 5000 ms t 32kpperase 32 kb block preprogram and erase time ? 400 600 5000 ms t 128kpperas e 128 kb block preprogram and erase time ? 800 1300 7500 ms t esus c c d erase suspend latency ? ? 30 30 s 1. typical program and erase times assume nominal supply values and operation at 25 c. 2. initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. 3. the maximum program and erase times occur after the specif ied number of program/erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. th is does not include software overhead. table 30. flash module life symbol c parameter conditions value unit min typ max p/e c c c number of program/erase cycles per block over the operating temperature range (t j ) 16 kb blocks 100000 ? ? cycle s 32 kb blocks 10000 100000 ? 128 kb blocks 1000 100000 ? retentio n c c c minimum data retention at 85 c average ambient temperature (1) blocks with 0?1000 p/e cycles 20 ? ? years blocks with 1001?10000 p/e cycles 10 ? ? blocks with 10001?100000 p/e cycles 5?? 1. ambient temperature averaged over dur ation of application, not to exceed recommended product operating temperature range. package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 70/117 doc id 14619 rev 12 ecc circuitry provides correction of single bit faults and is used to improve further automotive reliability results. some units will experience single bit corrections throughout the life of the product with no impact to product reliability. 3.19.2 flash power supply dc characteristics ta ble 32 shows the power supply dc characteristics on external supply. table 31. flash read access timing symbol c parameter conditions (1) 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified max unit f read cc p maximum frequency for flash reading 2 wait states 64 mhz c1 wait state40 c 0 wait states 20 table 32. flash memory power supply dc electrical characteristics symbol c parameter conditions (1) value uni t min typ max i fread (2) c c d sum of the current consumption on vdd_hv and vdd_bv on read access code flash memory module read f cpu = 64 mhz (3) ?1533 ma data flash memory module read f cpu = 64 mhz 3 ?1533 i fmod 2 c c d sum of the current consumption on vdd_hv and vdd_bv on matrix modification (program/erase) program/erase ongoing while reading code flash memory registers f cpu = 64 mhz 3 ?1533 ma program/erase ongoing while reading data flash memory registers f cpu = 64 mhz 3 ?1533 i flpw c c d sum of the current consumption on vdd_hv and vdd_bv during code flash memory low- power mode ??900 a during data flash memory low- power mode ??900 i fpwd c c d sum of the current consumption on vdd_hv and vdd_bv during code flash memory power-down mode ??150 a during data flash memory power-down mode ??150 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. this value is only relative to the actual duration of the read cycle 3. f cpu 64 mhz can be achieved only at up to 105 c spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 71/117 3.19.3 start-up/switch-off timings 3.20 electromagnetic compatibility (emc) characteristics susceptibility tests are performed on a sample basis during product characterization. 3.20.1 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note software techniques for improving microcontroller emc performance (an1015)). table 33. start-up time/switch-off time symbol c parameter conditions (1) value uni t min typ max t flarstexit c c t delay for flash module to exit reset mode code flash ? ? 125 s t data flash ? ? 125 t flalpexit c c t delay for flash module to exit low-power mode code flash ? ? 0.5 t data flash ? ? 0.5 t flapdexit c c t delay for flash module to exit power-down mode code flash ? ? 30 t data flash ? ? 30 t flalpentry c c t delay for flash module to enter low-power mode code flash ? ? 0.5 t data flash ? ? 0.5 t flapdentry c c t delay for flash module to enter power-down mode code flash ? ? 1.5 t data flash ? ? 1.5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 72/117 doc id 14619 rev 12 3.20.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec 61967-1 standard, which specifies the general conditions for emi measurements. 3.20.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. for more details, refer to the application note electrostatic discharge sensitivity measurement (an1181). table 34. emi radiated emission measurement (1)(2) symbol c parameter conditions value unit min typ max ? sr ? scan range ? 0.150 ? 1000 mhz f cpu sr ? operating frequency ? ? 64 ? mhz v dd_lv sr ? lv operating voltages ? ? 1.28 ? v s emi cc t peak level v dd = 5v, t a =25c, lqfp144 package test conforming to iec 61967-2, f osc = 8 mhz/f cpu = 64 mhz no pll frequency modulation ??18 db v 2% pll frequency modulation ??14 db v 1. emi testing and i/o port waveforms per iec 61967-1, -2, -4 2. for information on conducted emission and susceptibility measurement (norm iec 61967-4), please contact your local marketing representative. table 35. esd absolute maximum ratings (1) (2) symbol c ratings conditions clas s max value unit v esd(hbm) c c t electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) c c t electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) c c t electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the device no longer m eets the device specification requirements. complete dc parametric and functional test ing shall be performed per applic able device specification at room temperature followed by hot temperature, unless specified other wise in the device specification. spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 73/117 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin. a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.21 fast external crystal oscillator (4 to 16 mhz) electrical characteristics the device provides an oscillator/resonator driver. figure 13 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. ta ble 37 provides the parameter description of 4 mhz to 16 mhz crystals used for the design simulations. table 36. latch-up results symbol c parameter conditions class lu cc t static latch-up class t a = 125 c conforming to jesd 78 ii level a package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 74/117 doc id 14619 rev 12 figure 13. crystal oscillator and resonator connection scheme c2 c1 crystal xtal extal resonator xtal extal device device device xtal extal i r v dd 2. a series resistor may be required, according to crystal oscillator supplier recommendations. 1. xtal/extal must not be directly used to drive external circuits notes: table 37. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) (1) shunt capacitance between xtalout and xtalin c0 (2) (pf) 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 1. the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the ac / transient behavior depends upon them. 2. the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 75/117 figure 14. fast external crystal oscillator (4 to 16 mhz) timing diagram v fxoscop t fxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f fxosc s_mtrans bit (me_gs register) ?1? ?0? package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 76/117 doc id 14619 rev 12 table 38. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions (1) value unit min typ max f fxosc s r ? fast external crystal oscillator frequency ?4.0?16.0mhz g mfxosc c c c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 ? 8.2 ma/ v c c p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 ? 7.4 c c c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 ? 9.7 c c c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 ? 9.2 v fxosc c c t oscillation amplitude at extal f osc = 4 mhz, oscillator_margin = 0 1.3 ? ? v f osc = 16 mhz, oscillator_margin = 1 1.3 ? ? v fxosco p c c c oscillation operating point ? ? 0.95 ? v i fxosc (2) c c t fast external crystal oscillator consumption ??23ma t fxoscsu c c t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ?? 6 ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih s r p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd ?v dd +0.4 v v il s r p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.4 ? 0.35v dd v 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2. stated values take into account only analog module cons umption but not the digital contributor (clock tree and enabled peripherals) spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 77/117 3.22 slow external crystal oscillator (32 khz) electrical characteristics the device provides a low power oscillator/resonator driver. figure 15. crystal oscillator and resonator connection scheme figure 16. equivalent circuit of a quartz crystal osc32k_xtal osc32k_extal device c2 c1 crystal osc32k_xtal osc32k_extal resonator device note: osc32k_xtal/osc32k_extal must not be directly used to drive external circuits. c0 c2 c1 c2 r m c1 l m c m crystal table 39. crystal motional characteristics (1) symbo l parameter conditions value uni t min typ max l m motional inductance ? ? 11.796 ? kh c m motional capacitance ? ? 2 ? ff c1/c2 load capacitance at osc32k_xtal and osc32k_extal with respect to ground (2) ? 18 ? 28 pf package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 78/117 doc id 14619 rev 12 figure 17. slow external crystal oscillator (32 khz) timing diagram r m (3) motional resistance ac coupled @ c0 = 2.85 pf (4) ??65 k ac coupled @ c0 = 4.9 pf 4 ??50 ac coupled @ c0 = 7.0 pf 4 ??35 ac coupled @ c0 = 9.0 pf 4 ??30 1. crystal used: epson toyocom mc306 2. this is the recommended range of load capacitance at osc3 2k_xtal and osc32k_extal with respect to ground. it includes all the parasitics due to board traces, crystal and package. 3. maximum esr (r m ) of the crystal is 50 k 4. c0 includes a parasitic capac itance of 2.0 pf between osc32k_xtal and osc32k_extal pins table 39. crystal motional characteristics (1) (continued) symbo l parameter conditions value uni t min typ max oscon bit (osc_ctl register) t sxoscsu 1 v osc32k_xtal v sxosc valid internal clock 90% 10% 1/f sxosc 0 table 40. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions (1) value uni t min typ max f sxosc s r ? slow external crystal oscillator frequency ? 32 32.76 8 40 khz v sxosc c c t oscillation amplitude ? ? 2.1 ? v i sxoscbia s c c t oscillation bias current ? ? 2.5 ? a spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 79/117 3.23 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmpll) module to generate a fast system clock from the main oscillator driver. i sxosc c c t slow external crystal oscillator consumption ???8a t sxoscsu c c t slow external crystal oscillator start-up time ???2 (2) s 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. values are specified for no neighbor gpio pin activity. if oscillator is enabled (osc32k_xtal and osc32k_extal pins ), neighboring pins should not toggle. 2. start-up time has been measured with epson toyocom mc306 crystal. variation may be seen with other crystal. table 40. slow external crystal oscillator (32 khz) electrical characteristics (continued) symbol c parameter conditions (1) value uni t min typ max table 41. fmpll electrical characteristics symbol c parameter conditions (1) value uni t min typ max f pllin s r ? fmpll reference clock (2) ?4?64 mh z pllin s r ? fmpll reference clock duty cycle 2 ?40?60% f pllout c c d fmpll output clock frequency ? 16 ? 64 mh z f vco (3) c c p vco frequency without frequency modulation ? 256 ? 512 mh z c vco frequency with frequency modulation ? 245 ? 533 f cpu s r ? system clock frequency ? ? ? 64 mh z f free c c p free-running frequency ? 20 ? 150 mh z t lock c c p fmpll lock time stable oscillator (f pllin = 16 mhz) ? 40 100 s t stjit c c ? fmpll short term jitter (4) f sys maximum ?4 ? 4 % t ltjit c c ? fmpll long term jitter f pllin = 16 mhz (resonator) , f pllclk @ 64 mhz, 4000 cycles ? ? 10 ns i pll c c c fmpll consumption t a = 25 c ? ? 4 ma 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. pllin clock retrieved directly from fxosc clock. input c haracteristics are granted when os cillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and pllin . package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 80/117 doc id 14619 rev 12 3.24 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz fast internal rc oscillator. this is used as the default clock at the power-up of the device. 3. frequency modulation is considered 4% 4. short term jitter is measured on the clock rising edge at cycle n and n+4. table 42. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions (1) value uni t min typ max f firc c c p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mh z s r ? ? 12 20 i fircrun (2) c c t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a i fircpwd c c d fast internal rc oscillator high frequency current in power down mode t a = 125 c ? ? 10 a i fircstop c c t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ?1250? t fircsu c c c fast internal rc oscillator start-up time v dd = 5.0 v 10% ? 1.1 2.0 s fircpre c c t fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1?+1% firctri m c c t fast internal rc oscillator trimming step t a = 25 c ? 1.6 % fircvar c c p fast internal rc oscillator variation in overtemperature and supply with respect to f firc at t a =25c in high-frequency configuration ? ? 5?+5% 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this does not include consumption linked to clock tree togg ling and peripherals consumption when rc oscillator is on. spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 81/117 3.25 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz slow internal rc oscillator. this can be used as the reference clock for the rtc module. table 43. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions (1) value uni t min typ max f sirc c c p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz s r ? ? 100 ? 150 i sirc (2) c c c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu c c p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ?812s sircpre c c c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2?+2 % sirctrim c c c slow internal rc oscillator trimming step ??2.7? sircvar c c c slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a =55c in high frequency configuration high frequency configuration ? 10 ? +10 % 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. this does not include consumption linked to clock tree togg ling and peripherals consumption when rc oscillator is on. package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 82/117 doc id 14619 rev 12 3.26 adc electrical characteristics 3.26.1 introduction the device provides a 10-bit successive approximation register (sar) analog-to-digital converter. figure 18. adc characterist ic and error definitions 3.26.2 input impedance and adc accuracy in the following analysis, the input circuit corresponding to the precise channels is considered. (2) (1) (3) (4) (5) offset error (e o ) offset error (e o ) gain error (e g ) 1 lsb (ideal) 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve 1 lsb ideal = v dd_adc / 1024 v in(a) (lsb ideal ) code out spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 83/117 to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to be measured. the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being c s and c p2 substantially two switched capacitances, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s +c p2 equal to 3 pf, a resistance of 330 k is obtained (r eq = 1 / (f c (c s +c p2 )), where f c represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s +c p2 ) and the sum of r s + r f , the external circuit must be designed to respect the equation 4 : equation 4 equation 4 generates a constraint for external network design, in particular on a resistive path. v a r s r f + r eq --------------------- ? 1 2 -- -lsb < package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 84/117 doc id 14619 rev 12 figure 19. input equivalent circuit (precise channels) figure 20. input equivalent circuit (extended channels) r f c f r s r l r sw1 c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw1 : channel selection switch impedance r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 and c p2 ) c s : sampling capacitance r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a c p2 extended r sw2 switch r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw1 : channel selection switch impedance (two contributions, r sw1 and r sw2 ) r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 , c p2 and c p3 ) c s : sampling capacitance spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 85/117 a second aspect involving the capacitance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit in figure 19 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 21. transient behavior during sampling phase in particular two different transient periods can be distinguished: 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: v a v a1 v a2 t t s v cs voltage transient on c s v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 ) 1 r sw r ad + () = c p c s ? c p c s + --------------------- - ? package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 86/117 doc id 14619 rev 12 equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : equation 7 2. a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): equation 10 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. 1 r sw r ad + () < c s t s ? ? v a1 c s c p1 c p2 ++ () ? v a c p1 c p2 + () ? = 2 r l < c s c p1 c p2 ++ () ? 2 ? 8.5 r l c s c p1 c p2 ++ () ? ? = t s < v a2 c s c p1 c p2 c f +++ () ? v a c f ? v a1 +c p1 c p2 +c s + () ? = spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 87/117 figure 22. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 12 f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise v a2 v a ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? > package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 88/117 doc id 14619 rev 12 3.26.3 adc electrical characteristics table 44. adc input leakage current symbol c parameter conditions value uni t min typ max i lk g c c d input leakage current t a = ? 40 c no current injection on adjacent pin ?170 na dt a = 25 c ? 1 70 dt a =85 c ? 3 100 d t a = 105 c ?8200 p t a = 125 c ?45400 table 45. adc conversion characteristics symbol c parameter conditions (1) value unit min typ max v ss_adc sr ? voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ) (2) ? ? 0.1 ? 0.1 v v dd_adc sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?v dd ? 0.1 ? v dd +0.1 v v ainx sr ? analog input voltage (3) ?v ss_adc ? 0.1 ? v dd_adc +0.1 v f adc sr ? adc analog frequency ? 6 ? 32 + 4% mhz adc_sys sr ? adc digital clock duty cycle (ipg_clk) adclksel = 1 (4) 45 ? 55 % i adcpwd sr ? adc0 consumption in power down mode ???50a i adcrun sr ? adc0 consumption in running mode ???4ma t adc_pu sr ? adc power up delay ? ? ? 1.5 s t s cc t sampling time (5) f adc = 32 mhz, inpsamp = 17 0.5 ? s f adc = 6 mhz, inpsamp = 255 ? ? 42 t c cc p conversion time (6) f adc = 32 mhz, inpcmp = 2 0.625 ? s c s cc d adc input sampling capacitance ???3pf spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 89/117 c p1 cc d adc input pin capacitance 1 ???3pf c p2 cc d adc input pin capacitance 2 ???1pf c p3 cc d adc input pin capacitance 3 ???1pf r sw1 cc d internal resistance of analog source ???3k r sw2 cc d internal resistance of analog source ???2k r ad cc d internal resistance of analog source ???2k i inj sr ? input current injection current injection on one adc input, different from the converted one v dd = 3.3 v 10% ? 5? 5 ma v dd = 5.0 v 10% ? 5? 5 |inl| cc t absolute value for integral non-linearity no overload ? 0.5 1.5 lsb |dnl| cc t absolute differential non-linearity no overload ? 0.5 1.0 lsb |e o | cc t absolute offset error ? ? 0.5 ? lsb |e g | cc t absolute gain error ? ? 0.6 ? lsb tuep cc p total unadjusted error (7) for precise channels, input only pins without current injection ? 20.6 2 lsb t with current injection ? 33 tuex cc t total unadjusted error 7 for extended channel without current injection ? 31 3 lsb t with current injection ? 44 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2. analog and digital v ss must be common (to be tied together externally). 3. v ainx may exceed v ss_adc and v dd_adc limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff. 4. duty cycle is ensured by using system clock without prescaling. when adclksel = 0, the duty cycle is ensured by internal divider by 2. 5. during the sampling time the input capacitance c s can be charged/discharged by the ex ternal source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s . after the end of the sampling time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. 6. this parameter does not include the sampling time t s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 7. total unadjusted error: the maximum error that occurs without adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 45. adc conversion characteristics (continued) symbol c parameter conditions (1) value unit min typ max package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 90/117 doc id 14619 rev 12 3.27 on-chip peripherals 3.27.1 current consumption table 46. on-chip peripherals current consumption (1) symbol c parameter conditions typical value (2) uni t i dd_bv(can) c c t can (flexcan) supply current on vdd_bv bitrate: 500 kbyte/s total (static + dynamic) consumption: ? flexcan in loop-back mode ? xtal @ 8 mhz used as can engine clock source ? message sending period is 580 s 8 * f periph + 85 a bitrate: 125 kbyte/s 8 * f periph + 27 i dd_bv(emios) c c t emios supply current on vdd_bv static consumption: ? emios channel off ? global prescaler enabled 29 * f periph a dynamic consumption: ? it does not change varying the frequency (0.003 ma) 3 i dd_bv(sci) c c t sci (linflex) supply current on vdd_bv total (static + dynamic) consumption: ? lin mode ? baudrate: 20 kbyte/s 5 * f periph + 31 a i dd_bv(spi) c c t spi (dspi) supply current on vdd_bv ballast static consumption (only clocked) 1 a ballast dynamic consumption (continuous communication): ? baudrate: 2 mbit/s ? transmission every 8 s ? frame: 16 bits 16 * f periph i dd_bv(adc) c c t adc supply current on vdd_bv v dd =5.5 v ballast static consumption (no conversion) 41 * f periph a ballast dynamic consumption (continuous conversion) (3) 5 * f periph i dd_hv_adc(adc ) c c t adc supply current on vdd_hv_adc v dd =5.5 v analog static consumption (no conversion) 2 * f periph a analog dynamic consumption (continuous conversion) 75 * f periph + 32 i dd_hv(flash) c c t code flash + data flash supply current on vdd_hv v dd =5.5 v ?8.21ma i dd_hv(pll) c c t pll supply current on vdd_hv v dd =5.5 v ?30 * f periph a spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 91/117 3.27.2 dspi characteristics 1. operating conditions: t a = 25 c, f periph = 8 mhz to 64 mhz 2. f periph is an absolute value. 3. during the conversion, the total current consumption is give n from the sum of the static and dynamic consumption, i.e., (41 + 5) * f periph . table 47. dspi characteristics (1) no. symbol c parameter dspi0/dspi1 dspi2 unit min typ max min typ max 1t sck sr d sck cycle time master mode (mtfe = 0) 125 ? ? 333 ? ? ns d slave mode (mtfe = 0) 125 ? ? 333 ? ? d master mode (mtfe = 1) 83 ? ? 125 ? ? d slave mode (mtfe = 1) 83 ? ? 125 ? ? ?f dspi sr d dspi digital controller frequency ? ? f cpu ?? f cpu mhz ? t csc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1 0 master mode ? ? 130 (2) ?? 15 3 ns ? t asc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1 1 master mode ? ? 130 (3) ??130 3 ns 2 t cscext (4) sr d cs to sck delay slave mode 32 ? ? 32 ? ? ns 3 t ascext (5) sr d after sck delay slave mode 1/f dspi + 5 ? ? 1/f dspi + 5 ? ? ns package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 92/117 doc id 14619 rev 12 4t sdc cc d sck duty cycle master mode ? t sck /2 ? ? t sck /2 ? ns sr d slave mode t sck /2 ? ? t sck /2 ? ? 5t a sr d slave access time slave mode ? ? 1/f dspi + 70 ? ? 1/f dspi + 130 ns 6t di sr d slave sout disable time slave mode 7 ? ? 7 ? ? ns 7t pcsc sr d pcsx to pcss time 0 ? ? 0 ? ? ns 8t pasc sr d pcss to pcsx time 0 ? ? 0 ? ? ns 9t sui sr d data setup time for inputs master mode 43 ? ? 145 ? ? ns slave mode 5 ? ? 5 ? ? 10 t hi sr d data hold time for inputs master mode 0 ? ? 0 ? ? ns slave mode 2 (6) ?? 2 6 ?? 11 t suo (7) cc d data valid after sck edge master mode ? ? 32 ? ? 50 ns slave mode ? ? 52 ? ? 160 12 t ho 7 cc d data hold time for outputs master mode 0 ? ? 0 ? ? ns slave mode 8 ? ? 13 ? ? 1. operating conditions: c l = 10 to 50 pf, slew in = 3.5 to 15 ns. 2. maximum value is reached when csn pad is c onfigured as slow pad while sck pad is conf igured as medium. a positive value means that sck starts before csn is asserted. dspi2 has only slow sck available. 3. maximum value is reached when csn pad is configured as medium pad while sck pad is configured as slow. a positive value means that csn is deasserted before sck. dspi0 and dspi1 have only medium sck available. 4. the t csc delay value is configurable thr ough a register. when configuring t csc (using pcssck and cssck fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than t csc to ensure positive t cscext . 5. the t asc delay value is configurable thr ough a register. when configuring t asc (using pasc and asc fields in dspi_cta rx registers), delay between internal cs and internal sck must be higher than t asc to ensure positive t ascext . 6. this delay value corresponds to smpl_pt = 00b which is bit field 9 and 8 of the dspi_mcr. 7. sck and sout configured as medium pad table 47. dspi characteristics (1) (continued) no. symbol c parameter dspi0/dspi1 dspi2 unit min typ max min typ max spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 93/117 figure 23. dspi classic spi timing ? master, cpha = 0 figure 24. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference ta ble 47 . data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) note: numbers shown reference tab le 47 . package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 94/117 doc id 14619 rev 12 figure 25. dspi classic spi timing ? slave, cpha = 0 figure 26. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference table 47 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference tab le 4 7 . spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 95/117 figure 27. dspi modified transfer format timing ? master, cpha = 0 figure 28. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference table 47 . pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference ta ble 47 . package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 96/117 doc id 14619 rev 12 figure 29. dspi modified transfer format timing ? slave, cpha = 0 figure 30. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference tab le 4 7 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta ble 4 7 . spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 97/117 figure 31. dspi pcs strobe (pcss ) timing 3.27.3 nexus characteristics pcsx 7 8 pcss note: numbers shown reference ta ble 4 7 . table 48. nexus characteristics no. symbol c parameter value unit min typ max 1t tcyc cc d tck cycle time 64 ? ? ns 2t mcyc cc d mcko cycle time 32 ? ? ns 3t mdov cc d mcko low to mdo data valid ? ? 8 ns 4t mseov cc d mcko low to mseo_b data valid ? ? 8 ns 5t evtov cc d mcko low to evto data valid ? ? 8 ns 10 t ntdis cc d tdi data setup time 15 ? ? ns t ntmss cc d tms data setup time 15 ? ? ns 11 t ntdih cc d tdi data hold time 5 ? ? ns t ntmsh cc d tms data hold time 5 ? ? ns 12 t tdov cc d tck low to tdo data valid 35 ? ? ns 13 t tdoi cc d tck low to tdo data invalid 6 ? ? ns package pinouts and signal descriptions spc560b40x/50x, spc560c40x/50x 98/117 doc id 14619 rev 12 figure 32. nexus tdi, tms, tdo timing 3.27.4 jtag characteristics 10 tck tms, tdi tdo 11 12 note: numbers shown reference table 48 . table 49. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 64 ? ? ns 2t tdis cc d tdi setup time 15 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 4t tmss cc d tms setup time 15 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns 6t tdov cc d tck low to tdo valid ? ? 33 ns 7t tdoi cc d tck low to tdo invalid 6 ? ? ns spc560b40x/50x, spc560c40x/50x package pinouts and signal descriptions doc id 14619 rev 12 99/117 figure 33. timing diagram ? jtag boundary scan input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference table 49 . 3/5 2/4 7 6 package characteristics spc560b40x/50x, spc560c40x/50x 100/117 doc id 14619 rev 12 4 package characteristics 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 4.2 package mechanical data 4.2.1 lqfp64 figure 34. lqfp64 package mechanical drawing 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17 table 50. lqfp64 mechanical data symbol mm inches (1) min typ max min typ max a??1.6??0.063 a1 0.05 ? 0.15 0.002 ? 0.0059 a2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 ? 0.2 0.0035 ? 0.0079 d 11.8 12 12.2 0.4646 0.4724 0.4803 spc560b40x/50x, spc560c40x/50x package characteristics doc id 14619 rev 12 101/117 d1 9.8 10 10.2 0.3858 0.3937 0.4016 d3 ? 7.5 ? ? 0.2953 ? e 11.8 12 12.2 0.4646 0.4724 0.4803 e1 9.8 10 10.2 0.3858 0.3937 0.4016 e3 ? 7.5 ? ? 0.2953 ? e?0.5??0.0197? l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 ? 1 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 ccc ? ? 0.08 ? ? 0.0031 1. values in inches are converted fr om mm and rounded to 4 decimal digits. table 50. lqfp64 mechanical data (continued) symbol mm inches (1) min typ max min typ max package characteristics spc560b40x/50x, spc560c40x/50x 102/117 doc id 14619 rev 12 4.2.2 lqfp100 figure 35. lqfp100 package mechanical drawing table 51. lqfp100 mechanical data symbol mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 spc560b40x/50x, spc560c40x/50x package characteristics doc id 14619 rev 12 103/117 4.2.3 lqfp144 figure 36. lqfp144 package mechanical drawing e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.03.57.00.03.57.0 tolerance mm inches ccc 0.080 0.0031 1. values in inches are converted fr om mm and rounded to 4 decimal digits. table 51. lqfp100 mechanical data (continued) symbol mm inches (1) min typ max min typ max package characteristics spc560b40x/50x, spc560c40x/50x 104/117 doc id 14619 rev 12 table 52. lqfp144 mechanical data symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to 4 decimal digits. min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 ? 17.500 ? ? 0.6890 ? e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 ? 17.500 ? ? 0.6890 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 3.5 0.0 7.0 tolerance mm inches ccc 0.080 0.0031 spc560b40x/50x, spc560c40x/50x package characteristics doc id 14619 rev 12 105/117 4.2.4 lbga208 figure 37. lbga208 package mechanical drawing 1. the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of eac h corner is optional. table 53. lbga208 mechanical data symbol mm inches (1) notes min typ max min typ max a ? ? 1.70 ? ? 0.0669 (2) a1 0.30 ? ? 0.0118 ? ? ? a2 ? 1.085 ? ? 0.0427 ? ? a3 ? 0.30 ? ? 0.0118 ? ? a4 ? ? 0.80 ? ? 0.0315 ? b 0.50 0.60 0.70 0.0197 0.0236 0.0276 (3) 13 579111315 2 4 6 8 10 12 14 16 r l k t j n m p a b h g f d c e a1 corner index area (see note 1) bottom view b (208 balls) m m eee fff cab c seating plane a d d1 f e e1 f e a a1 a2 a3 a4 d ddd e b a c package characteristics spc560b40x/50x, spc560c40x/50x 106/117 doc id 14619 rev 12 d 16.80 17.00 17.20 0.6614 0.6693 0.6772 ? d1 ? 15.00 ? ? 0.5906 ? ? e 16.80 17.00 17.20 0.6614 0.6693 0.6772 ? e1 ? 15.00 ? ? 0.5906 ? ? e ? 1.00 ? ? 0.0394 ? ? f ? 1.00 ? ? 0.0394 ? ? ddd ? ? 0.20 ? ? 0.0079 ? eee ? ? 0.25 ? ? 0.0098 (4) fff ? ? 0.10 ? ? 0.0039 (5) 1. values in inches are converted from mm and rounded to four decimal digits. 2. lbga stands for l ow profile b all g rid a rray. ? low profile: the total profile height (dim a) is measured from the seating plane to the top of the component ? the maximum total package height is calculated by the following methodology: a2 typ + a1 typ + (a1 2 +a3 2 +a4 2 tolerance values) ? low profile: 1.20 mm < a 1.70 mm 3. the typical ball diameter before mounting is 0.60 mm. 4. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindric al tolerance zone eee perpendicular to datum c and located on true position with respect to datums a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. 5. the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is c ontained entirely in the respective zone eee above. the axis of each ball must lie simultaneously in both tolerance zones. table 53. lbga208 mechanical data (continued) symbol mm inches (1) notes min typ max min typ max spc560b40x/50x, spc560c40x/50x ordering information doc id 14619 rev 12 107/117 5 ordering information figure 38. commercial product code structure 1. lbga208 available only as development package for nexus2+ memory conditioning core family y = tray x = tape and reel 90 4e0 = 48 mhz eeprom 5v/3v 6e0 = 64 mhz eeprom 5v/3v b = ? 40 to 105 c c = ? 40 to 125 c l1 = lqfp64 l3 = lqfp100 l5 = lqfp144 b2 = lbga208 1 50 = 512 kb 44 = 384 kb 40 = 256 kb b = body c = gateway 0 = e200z0 spc56 = power architecture in 90nm temperature package custom vers. spc56 50 y 0b c l3 5e0 example code: product identifier ordering information spc560b40x/50x, spc560c40x/50x 108/117 doc id 14619 rev 12 appendix a abbreviations ta ble 54 lists abbreviations used but not defined elsewhere in this document. table 54. abbreviations abbreviation meaning cmos complementary metal?oxide?semiconductor cpha clock phase cpol clock polarity cs peripheral chip select evto event out mcko message clock out mdo message data116 out mseo message start/end out mtfe modified timing format enable sck serial communications clock sout serial data out tbd to be defined tck test clock input tdi test data input tdo test data output tms test mode select spc560b40x/50x, spc560c40x/50x revision history doc id 14619 rev 12 109/117 revision history table 55. document revision history date revision changes 04-apr-2008 1 initial release. 06-mar-2009 2 made minor editing and formatting changes to improve readability harmonized oscillator naming throughout document modified document title updated ?feature? on cover page replaced lfbga208 with lbga208 updated ?description? section updated ?spc560b40x/50x and spc560c40x/50x device comparison? table added ?block diagram? section section 3 ?package pinouts and signal descriptions?: ? removed signal descriptions (these are found in the device reference manual) updated ?lqfp 144-pin configuration (top view)? figure: ? replaced vpp with vss_hv on pin 18 ? added ma[1] as af3 for pc[10] (pin 28) ? added ma[0] as af2 for pc[3] (pin 116) ? changed description for pin 120 to ph[10] / gpio[122] / tms ? changed description for pin 127 to ph[9] / gpio[121] / tck ? replaced nmi[0] with nmi on pin 11 updated ?lqfp 100-pin configuration (top view)? figure: ? replaced vpp with vss_hv on pin 14 ? added ma[1] as af3 for pc[10] (pin 22) ? added ma[0] as af2 for pc[3] (pin 77) ? changed description for pin 81 to ph[10] / gpio[122] / tms ? changed description for pin 88 to ph[9] / gpio[121] / tck ? removed e1uc[19] from pin 76 ? replaced [11] with wkup[11] for pb[3] (pin 1) ? replaced nmi[0] with nmi on pin 7 updated ?lbga208 configuration? figure: ? changed description for ball b8 from tck to ph[9] ? changed description for ball b9 from tms to ph[10] ? updated descriptions for balls r9 and t9 added ?parameter classification? section and tagged parameters in tables where appropriate added ?nvusro register? section updated ?absolute maximum ratings? table ?recommended operating conditions? section : ? added note on ram data retention to end of section updated ?recommended operating conditions (3.3 v)? and ?recommended operating conditions (5.0 v)? added ?package thermal characteristics? section updated ?power considerations? section updated i/o input dc electrical characteristics definition? figure revision history spc560b40x/50x, spc560c40x/50x 110/117 doc id 14619 rev 12 06-mar-2009 2 (continued) updated tables: ? ?i/o input dc electrical characteristics? ? ?i/o pull-up/pull-down dc electrical characteristics? ? ?slow configuration output buffer electrical characteristics? ? ?medium configuration output buffer electrical characteristics? ? ?fast configuration output buffer electrical characteristics? added ?output pin transition times? section updated ?i/o consumption? table updated ?start-up reset requirements? figure updated ?reset electrical characteristics? table ?voltage regulator electrical characteristics? section: ? amended description of lv_pll ?voltage regulator capacitance connection? figure: ? exchanged position of symbols c dec1 and c dec2 updated tables? ? ?voltage regulator electrical characteristics? ? ?low voltage monitor electrical characteristics? ? ?low voltage power domain electrical characteristics? added ?low voltage monitor vs reset? figure updated ?flash memory electrical characteristics? section added ?electromagnetic compatibility (emc) characteristics? section updated ?fast external crystal oscillator (4 to 16 mhz) electrical characteristics? section updated ?slow external crystal oscillator (32 khz) electrical characteristics? section updated tables: ? ?fmpll electrical characteristics? ? ?fast internal rc oscillator (16 mhz) electrical characteristics? ? ?slow internal rc oscillator (128 khz) electrical characteristics? added ?on-chip peripherals? section added ?adc input leakage current? table updated ?adc conversion characteristics? table updated ?ecopack?? section corrected inverted column headings for typical and minimum dimensions in ?lqfp64 mechanical data? and ?lqfp100 mechanical data? tables added ?abbrevation? appendix 03-jun-2009 3 corrected ?commercial product code structure? figure table 55. document revision history (continued) date revision changes spc560b40x/50x, spc560c40x/50x revision history doc id 14619 rev 12 111/117 06-aug-2009 4 updated ? lbga208 configuration? figure ? absolute maximum ratings? table: ?v dd_adc , v in : changed min value for ?relative to v dd ? condition ?i corelv : added new row ?recommended operating conditions (5.0 v)? table: ?t a c-grade part, t j c-grade part, t a v-grade part, t j v-grade part, t a m-grade part, t j m-grade part : added new rows ? changed capacitance value in footnote ?output pin transition times? table: ? medium configuration: added condition for pad3v5v = 0 updated ?voltage regulator capacitance connection? ?voltage regulator electrical characteristics? table: ?c dec1 : changed min value ?i mreg: changed max value ?i dd_bv : added max value footnote ?low voltage monitor electrical characteristics? table: ?v lvdhv3h , v lvdhv5h : changed max value ?v lvdhv3l , v lvdhv5l : added max value updated ?low voltage power domain electrical characteristics? table ?flash module life? table: ? retention: deleted min value footnote for ?blocks with 100000 p/e cycles? ?fast external crystal oscillator (4 to 16 mhz) electrical characteristics? table: ?i fxosc : added typ value ?slow external crystal oscillator (32 khz) electrical characteristics? table ?v sxosc : changed typ value ?t sxoscsu : added max value footnote ?fmpll electrical characteristics? table ? t ltjit : added max value updated ?lqfp100 package mechanical drawing? table 55. document revision history (continued) date revision changes revision history spc560b40x/50x, spc560c40x/50x 112/117 doc id 14619 rev 12 20-jan-2010 5 table: ?absolute maximum ratings? ?v dd_bv , v dd_adc , v in : changed max value table: ?recommended operating conditions (3.3 v)? ?tv dd : deleted min value table: ?reset electrical characteristics? ? changed footnotes 2 and 5 table: ?voltage regulator electrical characteristics? ?c regn : changed max value ?c dec1 : split into 2 rows ? updated voltage values in footnote 3 table: ?low voltage monitor electrical characteristics? ? updated column conditions ?v lvdlvcorl , v lvdlvbkpl : changed min/max value table: ?program and erase specifications? ?t dwprogram : added initial max value table: ?flash module life? ? retention: changed min value for blocks with 100k p/e cycles table: ?flash power supply dc electrical characteristics? ?i fread , i fmod : added typ value ? added a footnote added section: ? nvusro[watchdog_en] field description? section 4.18: ?adc electrical characteristics? has been moved up in hierarchy (it was section 4.18.5). table: ? adc conversion characteristics? ?r ad : changed initial max value table: ?on-chip peripherals current consumption? ? removed min/max from the heading ? changed unit of measurement and consequently rounded the values 15-mar-2010 6 internal release. table 55. document revision history (continued) date revision changes spc560b40x/50x, spc560c40x/50x revision history doc id 14619 rev 12 113/117 22-jul-2010 7 changes between revisions 5 and 7 added lqfp64 package information updated the ?features? section. section ?introduction? ? relocated a note table: ?spc560b40x/50x and spc560c40x/50x device comparison? ? added footnote regarding sci and can added edma block in the ?spc560b40x/50x and spc560c40x/50x series block diagram? figure removed alternate function information from ?lqfp 100-pin configuration? and ?lqfp 100-pin configuration? figures. added ?functional port pin descriptions? table deleted the ?nvusro[watchdog_en] field description? section table: ?absolute maximum ratings? ? removed the min value of v in relative tio v dd table ?recommended operating conditions (3.3 v)? ?tv dd : made single row ?recommended operating conditions (5.0 v)? ? deleted t a c-grade part, t j c-grade part, t a v-grade part, t j v-grade part, t a m-grade part, t j m-grade part rows table: ?lqfp thermal characteristics? ? added more rows ? rounded the values removed table ?lbga208 thermal characteristics? table ?i/o input dc electrical characteristics? ?w fi : insered a footnote ?w nfi : insered a footnote table ?i/o consuption? ? removed i dynseg row ? added ?i/o weight ? table replaced ?nrstin ? with ?reset ? in the ?reset electrical characteristics? section. table ?voltage regulator electrical characteristics? ? updated the values ? removed i vregref and i vredlvd12 ? added a note about i dd_bc table: ?low voltage monitor electrical characteristics? ? changed min valuev lvdhv3l , from 2.7 to 2.6 ? inserted max value of v lvd lvc orl ? updated v porh values ? updated v lvd lvc or l value table ?low voltage power domain electrical characteristics? ? entirely updated table ?program and erase specifications? ? inserted t eslat row table ?flash power supply dc electrical characteristics? ? entirely updated table 55. document revision history (continued) date revision changes revision history spc560b40x/50x, spc560c40x/50x 114/117 doc id 14619 rev 12 22-jul-2010 7 (continued) table ?start-up time/switch-off time? ? entirely updated figures ?crystal oscillator and resonator connection scheme? ? relocated a note table ?slow external crystal oscillator (32 khz) electrical characteristics? ? removed g msxosc row ? inserted values of i sxoscbias table ?fmpll electrical characteristics? ? rounded the values of f vco table ?fast internal rc oscillator (16 mhz) electrical characteristics? ? entirely updated. table ?adc conversion characteristics? ? updated the description of the conditions of t adc_pu and t adc_s. ? added ?i adcpwd ? and ?i adcrun ? rows table ?dspi characteristics? ? entirely updated. updated ?order codes? table. figure ?commercial product code structure? ? replaced powerpc with ?power architecture?? in the product identifier ? removed the note about the condition from ?flash read access timing? table ? removed the notes that assert the values need to be confirmed before validation ? exchanged the order of ?lqfp 100-pin configuration? and ?lqfp 144-pin configuration? ? exchanged the order of ?lqfp 100-pin package mechanical drawing? and ?lqfp 144-pin package mechanical drawing? 25-nov-2010 8 editorial changes and improvements. in the ?spc560b40x/50x and spc560c40x/50x device comparison? table, changed the temperature value from 105 to 125 c, in the footnote regarding ?execution speed?. in the ?lqfp thermal characteristics? table, added values concerning lqfp64 package. in the ?medium configuration output buffer electrical characteristics? table: fixed a typo in last row of conditions column, there was i oh that now is i ol . in the ?reset electrical characteristics? table, changed the parameter classification tag for v ol and |i wpu |. in the ?low voltage monitor electrical characteristics? table, changed the max value of v lvdlvcorl from 1.5v to 1.15v. in the ?program and erase specifications? table, replaced ?t eslat ? with ?t esus ?. in the ?fmpll electrical characteristics? table, changed the parameter classification tag for f vco . table 55. document revision history (continued) date revision changes spc560b40x/50x, spc560c40x/50x revision history doc id 14619 rev 12 115/117 01-oct-2011 9 formatting and minor editorial changes throughout harmonized oscillator nomenclature device summary table: removed 384 kb code flash device versions device comparison table: changed temperature value in footnote 2 from 105 c to 125 c; removed 384 kb code flash device versions lqfp 64-pin configuration: renamed pin 6 from vpp_test to vss_hv removed ?pin muxing? section; added sections ?pad configuration during reset phases?, ?voltage supply pins?, ?pad types?, ?system pins,? ?functional ports?, and ?nexus 2+ pins? section ?nvusro register?: edited content to separate configuration into electrical parameters and digital functionality; updated footnote describing default value of ?1? in field descriptions nvusro[pad3v 5v] and nvusro[oscillator_margin] added section ?nvusro[watchdog_en] field description? recommended operating conditions (3.3 v) and recommended operating conditions (5.0 v): updated conditions for ambient and junction temperature characteristics i/o input dc electrical characteristics: updated i lkg characteristics section ?i/o pad current specification?: removed content referencing the i dynseg maximum value i/o consumption: replaced instances of ?root medium square? with ?root mean square? i/o weight: replaced instances of bit ?sre? with ?src?; added pads ph[9] and ph[10]; added supply segments; removed weight values in 64-pin lqfp for pads that do not exist in that package reset electrical characteristics: updated parameter classification for |i wpu | updated voltage regulator electrical characteristics section ?low voltage detector electrical characteristics?: changed title (was ?voltage monitor electrical characteristics?); added event status flag names found in rgm chapter of device reference manual to por module and lvd descriptions; replaced instances of ?low voltage monitor? with ?low voltage detector?; updated values for v lvdlvbkpl and v lvdlvcorl ; replaced ?lvd_digbkp? with ?lvdlvbkp? in note updated section ?power consumption? fast external crystal oscillator (4 to 16 mhz) electrical characteristics: updated parameter classification for v fxoscop crystal oscillator and resonator connection scheme: added footnote about possibility of adding a series resistor slow external crystal oscillator (32 khz) electrical characteristics: updated footnote 1 fmpll electrical characteristics: added short term jitter characteristics; inserted ??? in empty min value cell of t lock row section ?input impedance and adc accuracy?: changed ?v a /v a2 ? to ?v a2 /v a ? in equation 11 adc input leakage current: updated i lkg characteristics adc conversion characteristics: updated symbols on-chip peripherals current consumption: changed ?supply current on ?v dd_hv_adc? to ?supply current on? v dd_hv ? in i dd_hv(flash) row; updated i dd_hv(pll) value? was 3 * f periph , is 30 * f periph ; updated footnotes dspi characteristics: added rows t pcsc and t pasc added dspi pcs strobe (pcss) timing diagram updated order codes. 17-jan-2013 10 internal review. table 55. document revision history (continued) date revision changes revision history spc560b40x/50x, spc560c40x/50x 116/117 doc id 14619 rev 12 18-jan-2013 11 in the cover feature list, replaced ?system watchdog timer? with ?software watchdog timer? table 3 (spc560b40x/50x and spc560c40x/50x series block summary) , replaced ?system watchdog timer? with ?software watchdog timer? and specified autosar (automotive open system architecture) table 6 (functional port pin descriptions) , replaced vdd with vdd_hv figure 9 (voltage regulator capacitance connection) , updated pin name apperence renamed figure 10 (v dd_hv and v dd_bv maximum slope) (was ?vdd and vdd_bv maximum slope?) and replaced vdd_hv(min) with vporh(max) renamed figure 11 (v dd_hv and v dd_bv supply constraints during standby mode exit) (was ?vdd and vdd_bv supply constraints during standby mode exit?) table 13 (recommended operating conditions (3.3 v)) , added minimum value of t vdd and footnote about it. table 14 (recommended operating conditions (5.0 v)) , added minimum value of t vdd and footnote about it. section 3.17.1, voltage regulator electrical characteristics : replaced ?slew rate of v dd /v dd_bv ? with ?slew rate of both v dd_hv and v dd_bv ? replaced ?when standby mode is used, further constraints apply to the v dd /v dd_bv in order to guarantee correct regulator functionality during standby exit.? with ?when standby mode is used, further constraints are applied to the both v dd_hv and v dd_bv in order to guarantee correct regulator function during standby exit.? table 28 (power consumption on vdd_bv and vdd_hv) , updated footnotes of i ddmax and i ddrun stating that both currents are drawn only from the v dd_bv pin. table 32 (flash memory power supply dc electrical characteristics) , in the paremeter column replaced v dd_bv and v dd_hv respectively with vdd_bv and vdd_hv. table 46 (on-chip peripherals current consumption) , in the paremeter column replaced v dd_bv , v dd_hv and v dd_hv_adc respectively with vdd_bv, vdd_hv and vdd_hv_adc updated section 3.26.2, input impedance and adc accuracy table 47 (dspi characteristics) , modified symbol for t pcsc and t pasc 18-sep-2013 12 updated disclaimer. table 55. document revision history (continued) date revision changes spc560b40x/50x, spc560c40x/50x doc id 14619 rev 12 117/117 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? 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